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公开(公告)号：WO1989009520A1
公开(公告)日：1989-10-05
申请号：PCT/EP1988000272
申请日：1988-03-26
Applicant: BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE ... , ALCATEL N.V. , SWINNEN, Marc, Leander, Louis, Marie , BARRI, Peter, Irma, August
IPC: H04L07/02
CPC classification number: H04L7/0337
Abstract: Synchronizing circuit including a variable delay circuit (DLC) through which an input signal (DIN) is passed to adjust the phase of a regenerated output signal (DIN1) with respect to a clock signal (CL1) at the frequency of the input signal, and a decision circuit (DC) to adjust the variable delay (DL1/8) so that it covers half a period of the input signal and after having detected a predetermined lack of synchronism modifies the value of the variable delay such that this delay may then be adjusted to cover the second half of the period.
Abstract translation: 同步电路包括通过其输入输入信号（DIN）的可变延迟电路（DLC），以相对于输入信号的频率的时钟信号（CL1）调节再生输出信号（DIN1）的相位，以及 调整可变延迟（DL1 / 8）的判定电路（DC），使其覆盖输入信号的半个周期，并且在检测到预定的不同步之后修改可变延迟的值，使得该延迟可以是 调整到下半年。
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公开(公告)号：WO1988007298A1
公开(公告)日：1988-09-22
申请号：PCT/EP1988000212
申请日：1988-03-11
Applicant: BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE ... , ALCATEL N.V. , DEBUYSSCHER, Pierre, Leon
IPC: H04L11/20
CPC classification number: H04L49/103 , H04L49/505 , H04L49/557
Abstract: A switching system (SW) to transfer packets of digital signals having a header containing routing information from a plurality of input terminals (R1 to R16) to a plurality of output terminals (T1 to T16), the destination output terminal for a packet being selected according to the routing information of this packet. The system includes a plurality of memories (M1 to M8) which are each subdivided into a plurality of storage areas each associated to a respective output terminal, receiver circuits (RC1 to RC16) to divide each received packet into a plurality of sub-packets, control circuits (CC1 to CC8) and transmitter circuits (TC1 to TC16) to rebuilt a packet from its sub-packets. Under the control of the control circuits operating according to the routing information of a packet the sub-packets belonging to this packet are transmitted to respective ones of the memories and loaded into the storage area thereof corresponding to the destination output terminal.
Abstract translation: 一种用于将具有包含路由信息的报头的数字信号包从多个输入端（R1至R16）传送到多个输出端（T1至T16）的交换系统（SW），所选择的分组的目的地输出端 根据该报文的路由信息。 该系统包括多个存储器（M1至M8），每个存储器分别分成与相应的输出端子相关联的多个存储区域，接收器电路（RC1至RC16），用于将每个接收的分组划分成多个子分组， 控制电路（CC1至CC8）和发射机电路（TC1至TC16）从其子包重建数据包。 在根据分组的路由信息操作的控制电路的控制下，属于该分组的子分组被发送到相应的存储器，并被加载到与目的地输出终端对应的存储区域中。
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公开(公告)号：WO1990010984A1
公开(公告)日：1990-09-20
申请号：PCT/EP1989000281
申请日：1989-03-14
Applicant: BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE ... , ALCATEL N.V. , BARRI, Peter, Irma, August
IPC: H04L11/20
CPC classification number: H04L12/5602 , H04L2012/563 , H04L2012/5632 , H04L2012/5636
Abstract: Communication switching system wherein for each cell stream to be transmitted through a switching element a virtual path is established from an input link to an output link of this element on the basis of the individual bandwidth used by this cell stream and of the then calculated total bandwidth used on this output link. For each cell stream a maintenance cell containing the individual cell stream bandwidth is transmitted on the corresponding virtual path and by means of these maintenance cells the total bandwidth used on each output link is re-calculated and it is checked if it is equal to the above-mentioned calculated total bandwidth. The latter is adjusted if a difference is detected.
Abstract translation: 通信交换系统，其中对于要通过交换元件发送的每个信元流，根据该信元流使用的单独带宽和随后计算出的总带宽，从输入链路到该元件的输出链路建立虚拟路径 用于此输出链接。 对于每个小区流，包含单个小区流带宽的维护单元在相应的虚拟路径上传输，并且通过这些维护单元重新计算每个输出链路上使用的总带宽，并且检查其是否等于上述 计算总带宽。 如果检测到差异，则调整后者。
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公开(公告)号：WO1990009703A1
公开(公告)日：1990-08-23
申请号：PCT/EP1989000137
申请日：1989-02-07
Inventor： ALCATEL N.V. , BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE ... , WILLOCX, Eddie, Louis, Marie
IPC: H03F01/52
CPC classification number: H03F3/68 , H03F1/523 , H04M19/005
Abstract: The line circuit includes an amplifier arrangement with two amplifiers (LOA1/2) each able to sink current from an associated line conductor (L1/2) to a negative voltage (V-) and via a common transistor (T). Each amplifier has an individual overcurrent detection circuit (OCD1/2) and a individual current limiting circuit (CLC1/2). The detection circuits are coupled to the limiting circuits through a common detection circuit (OCD3) and a common gating circuit (GCI) which supplies an active output signal to the limiting circuits when both the amplifiers sink excessive currents.
Abstract translation: 线路电路包括具有两个放大器（LOA1 / 2）的放大器装置，每个放大器能够从相关的线路导体（L1 / 2）吸收电流到负电压（V-）并且经由公共晶体管（T）。 每个放大器都有一个单独的过流检测电路（OCD1 / 2）和一个单独的限流电路（CLC1 / 2）。 检测电路通过公共检测电路（OCD3）和公共选通电路（GCI）耦合到限制电路，公共选通电路（GCI）当两个放大器都吸收过多的电流时，向限制电路提供有源输出信号。
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公开(公告)号：WO1990007849A1
公开(公告)日：1990-07-12
申请号：PCT/EP1988001213
申请日：1988-12-24
Inventor： ALCATEL N.V. , BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE ... , BUSSCHAERT, Hans, Johan, Jozef , RABAEY, Dirk, Herman, Lutgardis, Cornelius , REUSENS, Peter, Paul, Frans
IPC: H04Q11/04
CPC classification number: H04Q11/0428 , H04L12/525
Abstract: A multi-standard communication adapter (MSRA) for interfacing a low speed communication device (TP), e.g. a user station, and a high speed communication device (NP), e.g. an Integrated Services Digital Network (ISDN). Both these communication devices are allowed to transmit signals having electrical and functional interface characteristics which may be chosen amongst a wide variety of possible electrical and functional interface characteristics. The communication adapter is integrated in an electronic chip and is able to perform the different rate adaptation schemes owing to its programmable constituent parts (TXFR, TXUS, RXUS, RXFR, BUSA, BAUDA). The programmation of the communication adapter is realized by means of a host microprocessor external (PP) to the chip and which may also be used to temporarily store data transmitted between the two communication devices as well as to transmit information to or receive information from these devices. The communication adapter further includes a Baudrate generator (BAUDA) to control the clock signal on the low speed side (TP) and means to perform a self-test.
Abstract translation: 用于连接低速通信设备（TP）的多标准通信适配器（MSRA），例如， 用户站和高速通信设备（NP），例如， 综合业务数字网（ISDN）。 这两个通信设备都允许发送具有电和功能接口特性的信号，这些信号可以在各种各样的可能的电和功能接口特性中选择。 通信适配器集成在电子芯片中，由于其可编程组成部分（TXFR，TXUS，RXUS，RXFR，BUSA，BAUDA）能够执行不同的速率适配方案。 通信适配器的编程通过对芯片的主机微处理器外部（PP）实现，并且还可以用于临时存储在两个通信设备之间传输的数据，以及向这些设备发送信息或从这些设备接收信息 。 通信适配器还包括用于控制低速侧（TP）上的时钟信号的波特率发生器（BAUDA）和进行自检的装置。
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Patent Agency Ranking
公开(公告)号：WO1990007777A1
公开(公告)日：1990-07-12
申请号：PCT/EP1988001215
申请日：1988-12-24
Applicant: ALCATEL N. V. , BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE ... , SCHMIT, Jean-Jacques
IPC: G11C07/00
Abstract: An asynchronous timing or control circuit (TIM) for a RAM memory applies a row selection (ROWD) signal to one end (WIO/WIN) of a selected memory row (WORD0/WORDN) and a corresponding control signal (WO0/WON) is collected at the other end (WO0/WON) of this row through a common NOR gate (04) with an input for each row. Since this control signal reflects the propagation time of a signal through the row, it is used to control the precharging (PRECHB) of the memory columns prior to any subsequent read or write operation, the latter using the same row selection signal.
Abstract translation: 用于RAM存储器的异步定时或控制电路（TIM）将所选择的存储器行（WORD0 / WORDN）的一行（WIO / WIN）的行选择（ROWD）信号应用到相应的控制信号（WO0 / WON） 在该行的另一端（WO0 / WON）通过公共NOR门（04）与每行的输入进行收集。 由于该控制信号反映了通过该行的信号的传播时间，所以它用于在任何后续读或写操作之前控制存储器列的预充电（PRECHB），后者使用相同的行选择信号。
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公开(公告)号：WO1989009521A1
公开(公告)日：1989-10-05
申请号：PCT/EP1988000273
申请日：1988-03-26
Applicant: BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE ... , ALCATEL N.V. , PAUWELS, Bart, Joseph, Gerard
IPC: H04L11/20
CPC classification number: H04L12/5601 , H04L12/433 , H04L49/106 , H04L49/309 , H04L2012/5651 , H04L2012/5674 , H04L2012/5681
Abstract: Communication switching element to switch M signal inputs (I(1) to I(M)) to any of N signal outputs (O(1) to O(N)) and comprising MN buffers (Q(11) to Q(MN)) which are arranged in a matrix of M rows and N columns. Each buffer is used to store cells during their transit from the associated input to the associated output.
Abstract translation: 通信开关元件，用于将M个信号输入（I（1）至I（M））切换到N个信号输出（O（1）至O（N））中的任一个，并且包括MN缓冲器（Q（11）至Q ），它们以M行和N列的矩阵排列。 每个缓冲区用于在从相关输入传输到相关输出的过程中存储单元。
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公开(公告)号：WO1988007297A1
公开(公告)日：1988-09-22
申请号：PCT/EP1988000178
申请日：1988-03-05
Applicant: BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE ... , ALCATEL N.V. , DE PRYCKER, Martin, Louis, Florence , RYCKEBUSCH, Mark, Lucien, Marie, Roger , BARRI, Peter, Irma, August
IPC: H04L11/20
CPC classification number: H04J3/0632 , G06F5/06 , G06F2205/061 , H04L7/10 , H04L12/56
Abstract: Asynchronous time division communication system wherein user stations (US1/2), each with an associated send and receive circuit (SEND1/2, REC1/2), are coupled with a packet switching network (PSN). Each send circuit includes a send clock (OSC) and each receive circuit is provided with a receive clock (POSC), controlling the reading of a packet buffer circuit (PFIFO), and with a computer (COMP) which regulates the receive clock (POSC) in such a way that the filling level of the buffer circuit remains substantially constant.
Abstract translation: 异步时分通信系统，其中具有相关联的发送和接收电路（SEND1 / 2，REC1 / 2）的用户站（US1 / 2）与分组交换网络（PSN）耦合。 每个发送电路包括发送时钟（OSC），并且每个接收电路都设置有接收时钟（POSC），控制分组缓冲电路（PFIFO）的读取，以及调节接收时钟（POSC）的计算机（COMP） ），使得缓冲电路的填充水平保持基本恒定。
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公开(公告)号：WO1988007295A1
公开(公告)日：1988-09-22
申请号：PCT/EP1988000177
申请日：1988-03-05
IPC: H04L11/16
CPC classification number: H04L12/437
Abstract: A ring communication network to transmit packets of data between terminal stations (U1 to U5) connected to this network via respective nodes (N1 to N5), each of these nodes comprising a first receiver circuit (RC0) and a first transmitter circuit (TC0) connected to segments of the network by respective terminals (R0 and T0), a second receiver circuit (RC1) and a second transmitter circuit (TC1) connected to the terminal station by respective terminals (R1 and T1), and control means (SB, SEC) comprising a multiplexer/demultiplexer circuit (SB) controlled by routing information contained in the packets and adapted to cyclically read (SEC) the first (RC0) and the second (RC1) receiver circuits and to transfer the packets stored in the read receiver circuit to the transmitter circuit (TC0/TC1) which is selected by these informations. This network may also include protection means (D1, IR, CR, IT, CT) against a faulty node.
Abstract translation: 一种环形通信网络，用于经由相应节点（N1至N5）连接到该网络的终端站（U1至U5）之间传送数据分组，这些节点中的每一个包括第一接收机电路（RC0）和第一发射机电路（TC0） 通过各个终端（R0和T0）连接到网络的段，通过各个终端（R1和T1）连接到终端站的第二接收机电路（RC1）和第二发射机电路（TC1）以及控制装置（SB， SEC）包括由分组中包含的路由信息控制的适于循环读取（SEC）第一（RC0）和第二（RC1）接收机电路并且传送存储在读取接收机中的分组的多路复用器/解复用器电路 电路由这些信息选择的发射机电路（TC0 / TC1）。 该网络还可以包括针对故障节点的保护装置（D1，IR，CR，IT，CT）。
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公开(公告)号：EP0699008A1
公开(公告)日：1996-02-28
申请号：EP95202121.0
申请日：1995-08-03
Inventor： Nederlof, Leo
CPC classification number: H04L45/00 , H04L45/28 , H04L69/40 , H04Q3/0079 , H04Q3/66 , H04Q2213/13141 , H04Q2213/13167
Abstract: A method is described for rerouting a data stream previously routed via a route through a switching network which has now failed. The method includes the steps of:
detecting the failure on a link (L19/L56) between first (SN1/SN5) and second (SN9/SN6) switching nodes in one of these switching nodes (SN1/SN5);
transmitting from this one switching node (SN1/SN5) a request message (REQ) with first (IDA) and second (IDB) address fields containing addresses of the first (1/5) and second (9/6) switching nodes, respectively;
in each switching node having received the request message (REQ) retransmitting it, until an alternative route for the data stream is found between two end switching nodes of said alternative route;
by one of these end switching nodes (SN1/SN5) chosen according to a predetermined rule after the alternative route has been found, allocating the data stream to this alternative route and transmitting it thereon.Abstract translation: 描述了一种方法，用于重新路由先前通过现在已经失败的交换网络路由的数据流。 该方法包括以下步骤：检测这些交换节点（SN1 / SN5）之一的第一（SN1 / SN5）和第二（SN9 / SN6）交换节点之间的链路（L19 / L56）的故障。 从该一个交换节点（SN1 / SN5）分别向包含第一（1/5）和第二（9/6）交换节点的地址的第一（IDA）和第二（IDB）地址字段发送请求消息（REQ） ; 在已经接收到重传它的请求消息（REQ）的每个交换节点中，直到在所述替代路由的两个端交换节点之间找到数据流的替代路由; 通过在找到替代路线之后根据预定规则选择的这些端交换节点（SN1 / SN5）中的一个，将数据流分配到该替代路由并在其上发送。
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