Abstract:
This cooling system for a plurality of circuit boards (3) carrying heat dissipating electric components (1, 2) comprises a network of metal rails (5, 7, 9, 11) intercoupling metal drain plates (4) of said boards and a heat exchanger (13), each of said metal rails including a heat pipe (19, 8, 10, 12).
Abstract:
A current control circuit for a circuit board carrying a parallel circuit comprising an input capacitor (Cb) shunted by an electronic circuit (IC) constituted by CMOS devices which do not dissipate power as long as no clock signal (CK) is applied to them. This control circuit limits voltage variations across other parallel circuits on other circuit boards already coupled to a power supply (PS), i.e. with charged input capacitors, when the present circuit board is newly coupled to this power supply or source. This is done by first intercoupling the parallel circuit and the source via a resistance and meanwhile preventing the clock signal (CK) from being applied to the electronic circuit (IC), and by allowing this clock signal to be applied to the electronic circuit (IC) during gradually increasing time periods (Th) after the resistance has been short-circuited.
Abstract:
The switching element is used for transferring, between X inputs (I1 - IX) and Y outputs (O1 - OY), cells divided into subcells of which only the first contains information about the destination output(s) of the cell. This switching element includes: a buffer memory (BM) with a plurality (C) of memory locations each having an address (K); and a memory management means (BMMU) for providing (FMLMC) addresses of free memory locations for storing the subcells therein, and for storing (BQ1 - BQY, SLM), under the form of linked lists, the memory location addresses used by the subcells, each list being associated to a distinct cell. The method is adapted to process variable length cells divided into subcells each containing a header (SCH) to distinguish a first/last subcell (FSC/LSC) of a cell from other subcells (ISC, LSC). Use is made of a subcell logic (SL) to detect the succession in either order of a subcell pertaining to a cell and of either a first/last subcell (FSC/LSC) of another cell or an idle subcell so as to identify the last/first subcell (LSC/FSC) of a cell.
Abstract:
A voltage selector uses a comparator (COMP) in order to clamp the potential (VSUB) of a p-doped substrate of a telecommunication Subscriber Line Integrated Circuit to the most negative voltage appearing at two input terminals (V1/2), one being supplied with the battery voltage and the other with a synthesized voltage, both varying within a relatively wide range with either one being able to be more negative than the other. With V1/2 connected to VSUB through respective DMOS transistors (N1/2), V1/2 also constitute the inputs of COMP whose outputs (C1/2) are connected to the gates of the DMOS transistors. The comparator is so designed as to allow a fast change-over of the opposite conductivity states of N1 and N2 whenever there is an inversion in the relative magnitudes of the V1 and V2 voltages, the voltage drop over a conductive N1/2 transistor being much lower than in the case of clamping diodes.
Abstract:
In this phase shifter from an input signal (IN) two intermediate signals (V1, V2) are derived with a mutual phase shift of about 90 degrees. These signals (V1, V2) are then converted in two other signals (V3, V4) with equal amplitudes and from the latter signals (V3, V4) sum (V5) and difference (V6) signals are then generated and converted again in two signals (OUT1, OUT2) with equal amplitudes. These signals constitute the output signals.
Abstract:
Resequencing system for a switching node (SN) of a cell switching system wherein cells or packets, of fixed or variable length, transmitted from an input to an output of a switching network (SNW), are subjected in the network to variable initial time delays for instance because they follow different paths therein. To restore at the output the sequence with which the cells were supplied to the input, the cells at the output are subjected to additional variable complementary time delays which are so chosen that for each cell the sum of the two time delays is substantially equal to a predetermined total value.
Abstract:
This system includes a main station (MS) and a plurality of substations (SX/SZ) which include each a transceiver and are all connected in parallel to first (UL) and second (DL) unidirectional links on which recurrent first and second cells of fixed length are transmitted in opposite direction. Each of these cells contains a plurality of signalling channels smaller than the number of substations. When a substation has to transmit data it starts an allocation procedure wherein the substation cooperates with the main station and by which a channel is allocated to it. Afterwards prior to transmitting the data the substation transmits a request signal in the allocated channel and starts transmission after having received from the main station a grant signal in the homologous signalling channel of a second cell. De-allocation of a channel occurs as soon as the latter is no longer needed.
Abstract:
In this system STM (Synchronous Transfer Mode) and ATM (Asynchronous Transfer Mode) cell streams are supplied to corresponding STM and ATM switching exchanges STME and ATME via the cascade connection of a multiplexer (MUX), a transmission link (L1) and a demultiplexer (DMUX). The MUX and DMUX are each constituted by a switching element with a plurality of inputs (I1/2; 13) and outputs (03, 04/5) coupled to a common switching means (SB1, TM1; SB2, TM2) via respective receiver (RC1/3) and transmitter (TC1/3) circuits. The common switching means samples the input cell streams at a frequency at least equal to the sum of the time slot frequencies of the time frames of the input cell streams. The time frames of the input and output cell streams are phase synchronous and the sampling of the input cell streams is performed in a predetermined order. The cells of the resultant (STM/ATM) cell stream are supplied to the transmitter circuits in function of their destination.
Abstract:
Statistical measurement equipment used in a communication system wherein individual cell streams with variable cell rates are multiplexed on a same link. The equipment includes a common circuit (CCC) with a first counter (CR1/8) counting a first number (A.B) of first cells of the multiplexed cell stream, and individual circuits (MMC, VMC, PMC) checking the mean, variance and peak of the probability distribution function of the variable cell rate. For instance, the MMC includes a second counter (MC) which counts the second cells of an individual cell stream and is reset by the first counter when the latter has counted the first number, the ratio of a second number of these cells and the first number constituting an expected value of the mean. As a consequence when the second number is counted this is indicative of the fact that the expected value of the mean is exceeded.
Abstract:
A documents singler which takes documents (4) from a stack and conveys them one by one to a user station via document retaining means (13). It includes a first conveyor belt (5) which has a document driving surface (8) facing the retaining means. The latter include a second belt (12) of which the external surface (11) is driven by the driving surface (8) and of which the inner surface (17) faces a braking surface (18). When more than one document try to pass between the first and the second belts, the one driven by the first belt exits first from the retaining means, the other or others being retained by the second belt which is no more driven by the first belt and is stopped by the braking surface against which it is pressed.