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    Noise shaper with shared and independent filters and multiple quantizers and data converters
    22.
    发明专利
    Noise shaper with shared and independent filters and multiple quantizers and data converters 审中-公开
    具有共享和独立过滤器和多个量化器和数据转换器的噪声形状

    公开(公告)号：JP2007006543A

    公开(公告)日：2007-01-11

    申请号：JP2006280760

    申请日：2006-10-13

    Applicant: Cirrus Logic Inc ,  シーラス ロジック,インコーポレイテッドCirrus Logic,Inc.

    Inventor： MELANSON JOHN LAURENCE

    IPC: H03M3/02 ,  H03M3/04 ,  H03M7/32 ,  H03M7/36

    CPC classification number: H03M7/3006 ,  H03M3/35 ,  H03M3/42 ,  H03M3/452 ,  H03M7/302 ,  H03M7/3037

    Abstract: PROBLEM TO BE SOLVED: To provide techniques which address the problem of mismatch between data conversion elements in DACs and ADCs.
    SOLUTION: The noise shaper includes first and second quantizers and first and second feedback paths each providing feedback from a corresponding quantizer output. A loop filter system implements a plurality of transfer functions including a first non-zero transfer function between the first feedback path and an input of the first quantizer, a second non-zero transfer function between the first feedback path and an input of the second quantizer, a third non-zero transfer function between the second feedback path and the input of the first quantizer and a fourth non-zero transfer between the second feedback path and the input of the second quantizer.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供解决DAC和ADC中的数据转换元件之间不匹配问题的技术。 解决方案：噪声整形器包括第一和第二量化器以及每个提供来自相应量化器输出的反馈的第一和第二反馈路径。 环路滤波器系统实现多个传递函数，包括在第一反馈路径和第一量化器的输入之间的第一非零传递函数，第一反馈路径和第二量化器的输入之间的第二非零传递函数 在所述第二反馈路径和所述第一量化器的输入之间的第三非零传递函数以及所述第二反馈路径和所述第二量化器的输入之间的第四非零传递。 版权所有（C）2007，JPO＆INPIT

    Spectrum smoothing filter
    23.
    发明专利
    Spectrum smoothing filter 审中-公开
    SPECTRUM SMOOTHING FILTER

    公开(公告)号：JP2005182998A

    公开(公告)日：2005-07-07

    申请号：JP2005000251

    申请日：2005-01-04

    Applicant: Cirrus Logic Inc ,  シーラス ロジック,インコーポレイテッドCirrus Logic,Inc.

    Inventor： BEHRENS RICHARD T ,  GLOVER NEAL ,  TRENT DUDLEY O ,  ARMSTRONG ALAN J ,  ZOOK CHRISTOPHER P ,  BLISS WILLIAM G

    IPC: G11B5/09 ,  G11B20/10 ,  H03H17/02 ,  H03H17/06 ,  H04B3/06

    CPC classification number: H03H17/06 ,  G11B5/09 ,  G11B20/10009 ,  H03H17/02

    Abstract: PROBLEM TO BE SOLVED: To provide a filter for compensating discrete secondary pulse formed in association with a data stream of discrete main pulses produced from a data read from magnetic media.
    SOLUTION: The filter's impulse response comprises a center coefficient with a side compensating coefficient for attenuating the secondary pulses when an input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter (378, 373, 375, 377, 390, 396, 451, 453, 455, 459) provides the two programmable delays using only one delay line (390).
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于补偿与从磁性介质读取的数据产生的离散主脉冲的数据流相关联形成的离散次级脉冲的滤波器。 滤波器的脉冲响应包括具有侧补偿系数的中心系数，用于当输入信号与脉冲响应卷积时衰减二次脉冲。 补偿系数的幅度和延迟可编程，并进行自适应调整，以优化给定环境的脉冲响应。 在传统的FIR实施例中，使用两条延迟线来产生中心系数和侧面补偿系数之间的两个可编程延迟。 在优选实施例中，IIR滤波器（378,373,375,377,390,396,451,453,455,459）仅使用一个延迟线（390）提供两个可编程延迟。 版权所有（C）2005，JPO＆NCIPI

    Improved fault tolerant sync mark detector for sampled amplitude magnetic recording
    25.
    发明专利
    Improved fault tolerant sync mark detector for sampled amplitude magnetic recording 有权
    改进的容错同步标记检测器，用于采样放大磁记录

    公开(公告)号：JP2009043408A

    公开(公告)日：2009-02-26

    申请号：JP2008273649

    申请日：2008-10-23

    Applicant: Cirrus Logic Inc ,  シーラス ロジック,インコーポレイテッドCirrus Logic,Inc.

    Inventor： ZOOK CHRISTOPHER P

    IPC: G11B20/14 ,  G11B5/012 ,  G11B20/10 ,  G11B20/18 ,  G11B27/30

    CPC classification number: G11B20/10055 ,  G11B5/012 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/1403 ,  G11B27/30 ,  G11B27/3027 ,  G11B2020/1476

    Abstract: PROBLEM TO BE SOLVED: To provide a sync mark detection method that uses information from a preamble and a sign of sampled data in order to further increase the fault tolerance of the sync mark detector.
    SOLUTION: Digital data comprise a preamble field, a sync mark following thereto and a data field following thereto. A timing recovery (28) in a read channel synchronizes to a phase and frequency of the preamble field, and the sync detector (A120) detects the sync mark in order to frame operation of RLL decoders (36, A122) for decoding the detected data field. To decrease the probability of early misdetection, the sync mark is chosen to have minimum correlation with shifted versions of the sync mark concatenated with the preamble field. To further increase the fault tolerance, the sync mark detector is enabled by timing recovery relative to an end of the preamble field.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种使用来自前导码的信息和采样数据的符号的同步标记检测方法，以进一步增加同步标记检测器的容错性。 解决方案：数字数据包括前导码字段，随后的同步标记和跟随它的数据字段。 读通道中的定时恢复（28）与前同步码字段的相位和频率同步，并且同步检测器（A120）检测同步标记，以便对用于解码检测数据的RLL解码器（36，A122）进行帧操作 领域。 为了降低早期错误检测的可能性，选择同步标记与与前同步码字段连接的同步标记的移位版本具有最小相关性。 为了进一步增加容错能力，同步标记检测器通过相对于前同步码字段的结束的定时恢复来启用。 版权所有（C）2009，JPO＆INPIT

    Analog-to-digital modulator
    26.
    发明专利
    Analog-to-digital modulator 审中-公开
    模拟数字调制器

    公开(公告)号：JP2008092606A

    公开(公告)日：2008-04-17

    申请号：JP2007332967

    申请日：2007-12-25

    Applicant: Cirrus Logic Inc ,  シーラス ロジック,インコーポレイテッドCirrus Logic,Inc.

    Inventor： TUCKER JOHN CHRISTOPHER

    IPC: H03M3/02 ,  H03M3/04

    CPC classification number: H03M3/32 ,  H03M3/424 ,  H03M3/448 ,  H03M3/452 ,  H03M3/454

    Abstract: PROBLEM TO BE SOLVED: To provide a method and system for operating two or more integrator amplifiers with different power supplies for a modulator of an analog-to-digital ("A/D") converter.
    SOLUTION: A first upstream integrator (INT1) is operated with one power supply, and the other downstream integrator(s) is/are operated with at least another power supply (INT2). The modulator has amplifiers with coefficient gains having values that are determined and set so that voltage levels for the at least another integrator are maintained within operating and output limits. An integrating coefficient gain (k1) for the first integrator is set to have a sufficiently large value so that an integrating capacitor can be made small for the one integrator. Another integrating coefficient gain (k2) for a second integrator is set to have a sufficiently small value so that an output voltage form the first integrator is sufficiently attenuated to a voltage value within an operating range of the second integrator.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于使用具有用于模拟数字（“A / D”）转换器的调制器的不同电源的两个或更多个积分放大器的方法和系统。

    解决方案：第一个上游积分器（INT1）由一个电源供电，另一个下游积分器至少与另一个电源（INT2）一起工作。 调制器具有放大器，其系数增益具有确定和设置的值，使得至少另一个积分器的电压电平保持在操作和输出限制内。 将第一积分器的积分系数增益（k1）设定为具有足够大的值，使得对于一个积分器可以使积分电容器较小。 将第二积分器的另一积分系数增益（k2）设定为具有足够小的值，使得形成第一积分器的输出电压充分衰减到第二积分器的工作范围内的电压值。 版权所有（C）2008，JPO＆INPIT

    Noise shaping circuit and method with feedback steering overload compensation and system using the same
    27.
    发明专利
    Noise shaping circuit and method with feedback steering overload compensation and system using the same 审中-公开
    噪声形成电路及其反馈转向过载补偿方法及其使用方法

    公开(公告)号：JP2007267434A

    公开(公告)日：2007-10-11

    申请号：JP2007192464

    申请日：2007-07-24

    Applicant: Cirrus Logic Inc ,  シーラス ロジック,インコーポレイテッドCirrus Logic,Inc.

    Inventor： MELANSON JOHN LAURENCE

    IPC: H03M7/32 ,  H03M3/04 ,  H03M7/36

    CPC classification number: H03M7/3011 ,  H03M7/3026 ,  H03M7/3033

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit whereby a noise shaper is immune to an input overload.
    SOLUTION: The noise shaper includes a first feedback loop for noise shaping a first feedback signal under normal operating conditions and having a first filter (201) with a first signal transfer function and a second feedback loop that is stable under overload conditions and has a second filter (202) having a second signal transfer function differing from the first signal transfer function. The noise shaper also includes an output circuit block including a quantizer (203) and steering circuitry (204). The quantizer (203) includes an input simultaneously responsive to outputs of the first (201) and second filters (202). The steering circuitry (204) steers a feedback signal from an output of the quantizer (203) to input of the first and second feedback loops.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种噪声整形器免于输入过载的方法和电路。 解决方案：噪声整形器包括用于在正常操作条件下对第一反馈信号进行噪声整形并具有第一信号传递函数的第一滤波器（201）和在过载条件下稳定的第二反馈环路的第一反馈环路，以及 具有不同于第一信号传递函数的第二信号传递函数的第二滤波器（202）。 噪声整形器还包括包括量化器（203）和转向电路（204）的输出电路块。 量化器（203）包括同时响应于第一（201）和第二滤波器（202）的输出的输入。 转向电路（204）将来自量化器（203）的输出的反馈信号转向第一和第二反馈回路的输入。 版权所有（C）2008，JPO＆INPIT

    Optical disk drive memory system, method for controlling movement of optical read head, and sliding mode controller
    29.
    发明专利
    Optical disk drive memory system, method for controlling movement of optical read head, and sliding mode controller 审中-公开
    光盘驱动存储器系统，用于控制光读头的运动的方法和滑模控制器

    公开(公告)号：JP2007035278A

    公开(公告)日：2007-02-08

    申请号：JP2006307240

    申请日：2006-11-13

    Applicant: Cirrus Logic Inc ,  シーラス ロジック,インコーポレイテッドCirrus Logic,Inc.

    Inventor： SUPINO LOUIS ,  ROMANO PAUL M ,  REIFF FRANCIS H

    IPC: G11B7/085 ,  G05B13/02 ,  G11B7/09

    CPC classification number: G11B7/0946 ,  G05B13/0255 ,  G11B7/08529 ,  G11B7/0908

    Abstract: PROBLEM TO BE SOLVED: To provide an optical disk drive servo control system having not so high sensitivity to a parameter change, capable of controlling transition better and reducing the performance cost of a complex adaptive linear controller. SOLUTION: The optical disk memory system is provided with a sliding mode controller 23 actuating an optical read head assembly on an optical disk during focus capture, focus tracking, track seek and center line tracking. This sliding mode controller operates while switching positive and negative feedback to follow a prescribed phase state locus by fitting a prescribed phase state (e.g. position error and speed of a read head). COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种对参数变化灵敏度不高的光盘驱动器伺服控制系统，能够更好地控制转换并降低复杂自适应线性控制器的性能成本。 解决方案：光盘存储器系统设置有滑动模式控制器23，其在聚焦捕获，聚焦跟踪，跟踪寻找和中心线跟踪期间致动光盘上的光学读取头组件。 该滑动模式控制器在通过拟合规定的相位状态（例如位置误差和读取头的速度）来切换正和负反馈以跟随规定的相位状态轨迹时进行操作。 版权所有（C）2007，JPO＆INPIT

    스위칭가능한 2차 재생 경로
    30.
    发明公开
    스위칭가능한 2차 재생 경로 审中-公开

    公开(公告)号：KR20200145865A

    公开(公告)日：2020-12-30

    申请号：KR20207037207

    申请日：2015-04-10

    Applicant: CIRRUS LOGIC INC

    Inventor： DAS TEJASVI ,  MELANSON JOHN L ,  TUCKER JOHN C ,  FEI XIAOFAN

    IPC: H03M1/66 ,  H03M1/00 ,  H03M1/08 ,  H03M1/68 ,  H03M1/70 ,  H03M1/78 ,  H03M3/00

    Abstract: 본개시내용의실시예들에따라, 프로세싱시스템은제 1 프로세싱경로및 제 2 프로세싱경로를포함하는복수의프로세싱경로들, 디지털-아날로그스테이지(stage) 출력부및 제어기를포함할수 있다. 제 1 프로세싱경로는디지털입력신호를제 1 중간아날로그신호로변환하기위한제 1 디지털-아날로그변환기를포함할수 있고, 제 1 디지털-아날로그변환기는고-전력상태및 저-전력상태에서동작하도록구성된다. 제 2 프로세싱경로는디지털입력신호를제 2 중간아날로그신호로변환하기위한제 2 디지털-아날로그변환기를포함할수 있다. 디지털-아날로그스테이지출력부는제 1 중간아날로그신호와제 2 중간아날로그신호의합을포함하는아날로그신호를생성하도록구성될수 있다. 제어기는디지털입력신호의크기가임계크기보다아래일때 제 1 디지털-아날로그변환기를저-전력상태에서동작하도록구성될수 있다.

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