公开(公告)号：KR20200145865A

公开(公告)日：2020-12-30

申请号：KR20207037207

申请日：2015-04-10

Applicant: CIRRUS LOGIC INC

Inventor： DAS TEJASVI ,  MELANSON JOHN L ,  TUCKER JOHN C ,  FEI XIAOFAN

IPC: H03M1/66 ,  H03M1/00 ,  H03M1/08 ,  H03M1/68 ,  H03M1/70 ,  H03M1/78 ,  H03M3/00

Abstract: 본개시내용의실시예들에따라, 프로세싱시스템은제 1 프로세싱경로및 제 2 프로세싱경로를포함하는복수의프로세싱경로들, 디지털-아날로그스테이지(stage) 출력부및 제어기를포함할수 있다. 제 1 프로세싱경로는디지털입력신호를제 1 중간아날로그신호로변환하기위한제 1 디지털-아날로그변환기를포함할수 있고, 제 1 디지털-아날로그변환기는고-전력상태및 저-전력상태에서동작하도록구성된다. 제 2 프로세싱경로는디지털입력신호를제 2 중간아날로그신호로변환하기위한제 2 디지털-아날로그변환기를포함할수 있다. 디지털-아날로그스테이지출력부는제 1 중간아날로그신호와제 2 중간아날로그신호의합을포함하는아날로그신호를생성하도록구성될수 있다. 제어기는디지털입력신호의크기가임계크기보다아래일때 제 1 디지털-아날로그변환기를저-전력상태에서동작하도록구성될수 있다.

公开(公告)号：GB2527677A

公开(公告)日：2015-12-30

申请号：GB201510578

申请日：2015-06-16

Applicant: CIRRUS LOGIC INC

Inventor： DAS TEJASVI ,  HE KU ,  MELANSON JOHN L

IPC: H03G3/00 ,  H03G3/30 ,  H03M1/70

Abstract: A circuit for providing an output signal to an audio transducer includes a digital path that receives a digital input signal. The digital path includes a selectable digital gain 12 and a DAC 14. The circuit also includes an analogue signal path that receives a converted signal from the DAC 14 and has a selectable analogue gain 16. Responsive to the signal level, a controller 20 predicts the occurrence of an event for changing the digital gain 12 and the analogue gain 16. Having predicted the need to change the gain settings, the controller 20 adjusts the gain near a zero crossing of the signal. The adjustment of gain in both the digital and analogue portions of the signal path allows noise and dynamic range to be improved. The invention aims to minimise audio artefacts such as clicks and pops, by switching the gains at zero crossings of the signal. The controller 16 may also predict the peak trend of a signal envelope (fig.4) and adjust the gain settings accordingly to prevent clipping.

公开(公告)号：GB2527637A

公开(公告)日：2015-12-30

申请号：GB201506258

申请日：2015-04-13

Applicant: CIRRUS LOGIC INC

Inventor： DAS TEJASVI ,  MELANSON JOHN L ,  TUCKER JOHN C ,  FEI XIAOFAN

IPC: H03M1/66 ,  H03M3/02

Abstract: At high digital input signal magnitudes, a controller 20 selects a sigma-delta DAC circuit 12A with good linearity and low noise, while at low signal magnitudes the controller 20 selects a DAC circuit 13A with low power consumption. The channels may be weighted (44,46, figure 4) in a complementary fashion in dependence on the input signal magnitude. In a multi-stage noise shaping (MASH) arrangement (figure 5), the input signal for the low power DAC circuit is a quantization error signal from a digital delta sigma modulator. The digital input signal may be subject to a low pass filter (72, figure 6) in the higher power DAC channel, a high frequency residue being generated by a subtraction circuit (86, figure 6) and fed to the low power DAC.

公开(公告)号：WO2016040171A4

公开(公告)日：2016-07-07

申请号：PCT/US2015048609

申请日：2015-09-04

Applicant: CIRRUS LOGIC INC

Inventor： HE KU ,  DAS TEJASVI ,  MELANSON JOHN L ,  SATOSKAR ANIRUDDHA

IPC: H03G3/30

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.

Abstract translation: 根据本公开的实施例，控制电路可以被配置为响应于在具有模拟路径部分和数字信号路径部分的信号路径的增益模式之间切换的指示，切换模拟信号路径部分的可选模拟增益 在第一模拟增益和第二模拟增益之​​间切换路径部分，在第一数字增益和第二数字增益之间切换数字信号路径部分的可选数字增益，其中第一模拟增益和第一数字增益的乘积近似于 等于第二模拟增益和第二数字增益的乘积，并且由于信号路径的增益模式之间的切换而控制信号路径的模拟响应，以减少输出信号中出现的音频伪像的出现。

公开(公告)号：WO2016040171A3

公开(公告)日：2016-05-06

申请号：PCT/US2015048609

申请日：2015-09-04

Applicant: CIRRUS LOGIC INC

Inventor： HE KU ,  DAS TEJASVI ,  MELANSON JOHN L ,  SATOSKAR ANIRUDDHA

IPC: H03G3/30

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.

Abstract translation: 根据本公开的实施例，控制电路可以被配置为响应于在具有模拟路径部分的信号路径的增益模式和数字信号路径部分之间切换的指示，切换模拟的可选择的模拟增益 在第一模拟增益和第二模拟增益之​​间的路径部分，在第一数字增益和第二数字增益之间切换数字信号路径部分的可选数字增益，其中第一模拟增益和第一数字增益的乘积近似 等于第二模拟增益和第二数字增益的乘积，并且作为信号路径的增益模式之间的切换的结果，控制信号路径的模拟响应以减少存在于输出信号中的音频伪像的出现。