公开(公告)号：US06354916B1

公开(公告)日：2002-03-12

申请号：US09544558

申请日：2000-04-06

Applicant: Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

Inventor： Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

IPC: B24B100

CPC classification number: B24B37/042 ,  C25D3/38 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A modified plating solution that can be used to electroplate a high quality conductive material that can be effectively polished and planarized includes (1) a solvent, (2) an ionic species of the conductive material to be deposited, (3) at least one additive to improve electrical and structural properties, and (4) a modifying agent.

公开(公告)号：US08816505B2

公开(公告)日：2014-08-26

申请号：US13193814

申请日：2011-07-29

Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

IPC: H01L23/48 ,  H01L21/283

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Abstract translation: 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

公开(公告)号：US08742541B2

公开(公告)日：2014-06-03

申请号：US13182890

申请日：2011-07-14

Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia ,  Vage Oganesian

Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia ,  Vage Oganesian

IPC: H01L21/02 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L23/642 ,  H01G4/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/16 ,  H01L28/40 ,  H01L28/91 ,  H01L28/92 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape.

Abstract translation: 电容器可以包括具有第一表面的基板，远离第一表面的第二表面，以及在第一和第二表面之间延伸的通孔，第一和第二金属元件以及将第一和第二表面分离和绝缘的电容器介电层 至少在通孔内的金属元​​件彼此之间。 第一金属元件可以在第一表面暴露并且可以延伸到通孔中。 第二金属元件可以在第二表面处露出并且可以延伸到通孔中。 第一和第二金属元件可以电连接到第一和第二电位。 电容器介电层可以具有起伏的形状。

公开(公告)号：US08728934B2

公开(公告)日：2014-05-20

申请号：US13168839

申请日：2011-06-24

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。 另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US20130014978A1

公开(公告)日：2013-01-17

申请号：US13183870

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

IPC: H05K1/09 ,  B05D1/36 ,  B05D5/12

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/056 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/013 ,  H05K1/09 ,  H05K3/4007 ,  H05K2201/032 ,  H05K2201/0326 ,  H05K2201/0338

Abstract: Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer.

Abstract translation: 用于电气应用的阻隔层。 在一些实施例中，阻挡层是层压阻挡层。 在一些实施例中，阻挡层包括梯度阻挡层。

公开(公告)号：US20120319282A1

公开(公告)日：2012-12-20

申请号：US13164448

申请日：2011-06-20

Applicant: Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US07476304B2

公开(公告)日：2009-01-13

申请号：US10947628

申请日：2004-09-21

Applicant: Jalal Ashjaee ,  Boguslaw Nagorski ,  Bulent M. Basol ,  Homayoun Talieh ,  Cyprian Uzoh

Inventor： Jalal Ashjaee ,  Boguslaw Nagorski ,  Bulent M. Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC: C25D17/00 ,  C25D5/00

CPC classification number: C25F7/00 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885

Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.

Abstract translation: 通过提供具有正面与工件正面的阳极区域并将工件正面与至少一个电气电连接的阳极进行导电材料沉积在导电材料上或从半导体工件的工件正面去除导电材料 通过将电触点和工件正面推入彼此靠近，在阳极区域外部接触。 在阳极和电接触之间施加电位，并且工件相对于阳极和电触点移动。 因此允许在工件正面侧面上进行全面电镀或电解抛光。

公开(公告)号：US07378004B2

公开(公告)日：2008-05-27

申请号：US10152793

申请日：2002-05-23

Applicant: Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

Inventor： Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

IPC: B24D11/00 ,  C25D5/22 ,  C25F3/00 ,  H01L21/3063

CPC classification number: B24B37/26 ,  B23H5/08 ,  C25D17/001 ,  C25D17/14

Abstract: An apparatus capable of assisting in controlling an electrolyte flow and an electric field distribution used for processing a substrate is provided. It includes a rigid member having a top surface of a predetermined shape and a bottom surface. The rigid member contains a plurality of channels, each forming a passage from the top surface to the bottom surface, and each allowing the electrolyte and electric field flow therethrough. A pad is attached to the rigid member via a fastener. The pad also allows for electrolyte and electric field flow therethrough to the substrate.

Abstract translation: 提供一种能够辅助控制用于处理基板的电解质流动和电场分布的装置。 它包括具有预定形状的顶表面和底表面的刚性构件。 刚性构件包括多个通道，每个通道形成从顶表面到底表面的通道，并且每个通道允许电解质和电场流过其中。 垫通过紧固件附接到刚性构件。 衬垫还允许电解质和电场流过衬底。

公开(公告)号：US07309413B2

公开(公告)日：2007-12-18

申请号：US10459321

申请日：2003-06-10

Applicant: Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

Inventor： Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

IPC: C25D5/04 ,  C25D7/12 ,  C25F3/12

CPC classification number: B23H3/04 ,  B23H5/08 ,  C25D5/08 ,  C25D17/00 ,  C25D17/001 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.

Abstract translation: 可以通过包括第一和第二导电元件的特定装置来提供导电材料在包含导电材料的电解质的衬底的包括半导体晶片的表面上的基本均匀沉积。 第一导电元件可以具有相同或不同构造的多个电触点，或者可以是导电焊盘的形式，并且可以在基本上所有的衬底表面上与衬底表面接触或以其他方式电互连。 当在电解质与衬底表面和第二导电元件物理接触的同时在第一和第二导电元件之间施加电势时，导电材料沉积在衬底表面上。 可以使施加在阳极和阴极之间的电压的极性反转，从而可以对沉积的导电材料进行电蚀刻。

公开(公告)号：US07201829B2

公开(公告)日：2007-04-10

申请号：US09960236

申请日：2001-09-20

Applicant: Bulent M. Basol ,  Cyprian Uzoh ,  Jeff A. Bogart

Inventor： Bulent M. Basol ,  Cyprian Uzoh ,  Jeff A. Bogart

IPC: C25F3/16 ,  C25F5/00 ,  C25D17/00

CPC classification number: H01L21/76879 ,  B24B37/042 ,  C25D5/02 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D17/001 ,  C25F7/00 ,  H01L21/2885

Abstract: The present invention includes a mask plate design that includes at least one or a plurality of channels portions on a surface of the mask plate, into which electrolyte solution will accumulate when the mask plate surface is disposed on a surface of wafer, and out of which the electrolyte solution will freely flow. There are also at least one or a plurality of polish portions on the mask plate surface that allow for polishing of the wafer when the mask plate surface is disposed on a surface of wafer.

Abstract translation: 本发明包括掩模板设计，其包括在掩模板的表面上的至少一个或多个通道部分，当掩模板表面设置在晶片的表面上时，电解质溶液将积聚在其中，并且其中 电解液会自由流动。 掩模板表面上还有至少一个或多个抛光部分，当掩模板表面设置在晶片的表面上时，允许抛光晶片。