公开(公告)号：US08609540B2

公开(公告)日：2013-12-17

申请号：US13164448

申请日：2011-06-20

Applicant: Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC: H01L21/32

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US20060219573A1

公开(公告)日：2006-10-05

申请号：US11445594

申请日：2006-06-01

Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

IPC: B23H3/00

CPC classification number: B24B37/20 ,  B24B37/046 ,  B24B37/24 ,  B24B37/26 ,  C25D5/06 ,  C25D17/001 ,  C25D17/14 ,  C25F7/00 ,  H01L21/2885 ,  H01L21/76877

Abstract: The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.

Abstract translation: 本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。 这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。 在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上， 在工件和阳极之间施加电位差。 在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。 在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

公开(公告)号：US20060070885A1

公开(公告)日：2006-04-06

申请号：US11295014

申请日：2005-12-06

Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

IPC: C25D5/02 ,  C25D5/48

CPC classification number: C25D5/00 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1848 ,  C23C18/31 ,  C25D5/02 ,  C25D5/10 ,  C25D5/22 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L24/11 ,  H01L2221/1089 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3011

Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

公开(公告)号：US06974769B2

公开(公告)日：2005-12-13

申请号：US10663318

申请日：2003-09-16

Applicant: Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

Inventor： Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/7684

Abstract: Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d1≦0.5d2, with d1 being the first layer thickness and d2 being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d1≦0.3d2.

Abstract translation: 通过特定的工艺制造衬底上的绝缘体层的特征的导电结构。 在该过程中，将导电材料层施加在绝缘体层上，使得导电材料层覆盖与特征相邻的场区域并填充特征本身。 然后通过退火导电材料层来建立覆盖场区的导电材料与填充特征的导电材料之间的晶粒尺寸差。 然后去除过量的导电材料以露出场区并留下导电结构。 施加导电材料层以在场区域上限定第一层厚度，并且在特征中和之上限定第二层厚度。 这些厚度的尺寸使得其中d 1是第一层厚度，d 2 <2 < / SUB>为第二层厚度。 优选地，第一层厚度和第二层厚度的尺寸被确定为使得d 1 = 0.3D 2。

公开(公告)号：US06969456B2

公开(公告)日：2005-11-29

申请号：US10041029

申请日：2001-12-28

Applicant: Konstantin Volodarsky ,  Boguslaw A. Nagorski ,  Rimma Volodarsky ,  Douglas W. Young ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Konstantin Volodarsky ,  Boguslaw A. Nagorski ,  Rimma Volodarsky ,  Douglas W. Young ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D7/12 ,  H01L21/00 ,  H01L21/02 ,  H01L21/3063 ,  C25F3/00 ,  B08B3/04

CPC classification number: H01L21/6719 ,  C25D7/12 ,  C25D17/001 ,  H01L21/67028 ,  Y10S134/902

Abstract: The present invention relates to a containment chamber that is used for carrying out multiple processing steps such as depositing on, polishing, etching, modifying, rinsing, cleaning, and drying a surface on the workpiece. In one example of the present invention, the chamber is used to electro chemically mechanically deposit a conductive material on a semiconductor wafer. The same containment chamber can then be used to rinse and clean the same wafer. As a result, the present invention eliminates the need for separate processing stations for depositing the conductive material and cleaning the wafer. Thus, with the present invention, costs and physical space are reduced while providing an efficient apparatus and method for carrying out multiple processes on the wafer surface using a containment chamber.

Abstract translation: 本发明涉及一种用于进行多个处理步骤的容纳室，例如沉积，抛光，蚀刻，改性，漂洗，清洁和干燥工件上的表面。 在本发明的一个实例中，室用于在半导体晶片上化学机械地沉积导电材料。 然后可以使用相同的容纳室来冲洗和清洁相同的晶片。 结果，本发明消除了对用于沉积导电材料和清洁晶片的单独处理站的需要。 因此，利用本发明，降低了成本和物理空间，同时提供了使用容纳室在晶片表面上执行多个工艺的有效的装置和方法。

公开(公告)号：US20050029123A1

公开(公告)日：2005-02-10

申请号：US10637731

申请日：2003-08-08

Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Halit Yakupoglu

Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Halit Yakupoglu

IPC: H01L21/321 ,  B29C71/02 ,  B05D5/12

CPC classification number: H01L21/32125

Abstract: The methods and systems described provide for radiation assisted material deposition, removal, and planarization at a surface, edge, and/or bevel of a workpiece such as a semiconductor wafer. Exemplary processes performed on a workpiece surface having topographical features include radiation assisted electrochemical material deposition, which produces an adsorbate layer outside of the features to suppress deposition outside of the features and to encourage, through charge conservation, deposition into the features to achieve, for example, a planar surface profile. A further exemplary process is radiation assisted electrochemical removal of material, which produces an adsorbate layer in the features to suppress removal of material from the features and to encourage, through charge conservation, removal of material outside of the features so that, for example, a planar surface profile is achieved.

Abstract translation: 所描述的方法和系统提供了诸如半导体晶片的工件的表面，边缘和/或斜面处的辐射辅助材料沉积，去除和平坦化。 在具有形貌特征的工件表面上执行的示例性工艺包括辐射辅助电化学材料沉积，其在特征之外产生吸附物层以抑制特征外的沉积，并且通过电荷保存沉积到特征中以实现例如 ，平面表面轮廓。 进一步的示例性方法是材料的辐射辅助电化学去除，其在特征中产生吸附物层以抑制材料从特征中的去除并且通过电荷保持除去特征外的材料，从而例如， 实现了平面表面轮廓。

公开(公告)号：US06773576B2

公开(公告)日：2004-08-10

申请号：US10251377

申请日：2002-09-20

Applicant: Rimma Volodarsky ,  Konstantin Volodarsky ,  Cyprian Uzoh ,  Homayoun Talieh ,  Douglas W. Young

Inventor： Rimma Volodarsky ,  Konstantin Volodarsky ,  Cyprian Uzoh ,  Homayoun Talieh ,  Douglas W. Young

IPC: C25F302

CPC classification number: C25D17/14 ,  C25F7/00

Abstract: A particular anode assembly can be used to supply a solution for any of a plating operation, a planarization operation, and a plating and planarization operation to be performed on a semiconductor wafer. The anode assembly includes a rotatable shaft disposed within a chamber in which the operation is performed, an anode housing connected to the shaft, and a porous pad support plate attached to the anode housing. The support plate has a top surface adapted to support a pad which is to face the wafer, and, together with the anode housing, defines an anode cavity. A consumable anode may be provided in the anode cavity to provide plating material to the solution. A solution delivery structure by which the solution can be delivered to said anode cavity is also provided. The solution delivery structure may be contained within the chamber in which the operation is performed. A shield can also be mounted between the shaft and an associated spindle to prevent leakage of the solution from the chamber.

Abstract translation: 可以使用特定的阳极组件来提供用于在半导体晶片上进行的电镀操作，平面化操作和电镀和平面化操作中的任何一种的解决方案。 阳极组件包括设置在其中执行操作的室内的可旋转轴，连接到轴的阳极壳体和附接到阳极壳体的多孔垫支撑板。 支撑板具有适于支撑面向晶片的焊盘的顶表面，并且与阳极壳体一起限定阳极腔。 可以在阳极腔中设置消耗性阳极以向溶液提供电镀材料。 还提供了可以将溶液输送到所述阳极腔的溶液输送结构。 溶液输送结构可以包含在进行操作的室内。 护罩还可以安装在轴和相关主轴之间，以防止溶液从腔室泄漏。

公开(公告)号：US06582579B1

公开(公告)日：2003-06-24

申请号：US09534704

申请日：2000-03-24

Applicant: Cyprian Uzoh

Inventor： Cyprian Uzoh

IPC: C25D502

CPC classification number: H01L21/76877 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76892

Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.

Abstract translation: 本发明涉及修复半导体衬底上的缺陷的方法。 这是通过在空腔中的缺陷部分中选择性地沉积导电材料而实现的，同时从衬底的场区域去除残余部分。 根据本发明的另一种方法包括在衬底的顶表面上形成均匀的导电材料覆盖层。 本发明还公开了一种在衬底的第一导电材料上沉积第二导电材料的方法。

公开(公告)号：US06482307B2

公开(公告)日：2002-11-19

申请号：US09735546

申请日：2000-12-14

Applicant: Jalal Ashjaee ,  Boguslaw A. Nagorski ,  Bulent M. Basol ,  Homayoun Talieh ,  Cyprian Uzoh

Inventor： Jalal Ashjaee ,  Boguslaw A. Nagorski ,  Bulent M. Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC: C25D518

CPC classification number: C25D17/001 ,  C25D7/123 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

Abstract: Deposition of conductive material on or removal of conductive material from a wafer frontal side of a semiconductor wafer is performed by providing an anode having an anode area which is to face the wafer frontal side, and electrically connecting the wafer frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the wafer frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the wafer is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the wafer frontal side surface, in its entirety, is thus permitted.

Abstract translation: 通过提供具有面向晶片正面的阳极区域的阳极和将晶片正面与至少一个电气电连接来进行导电材料沉积在半导体晶片的晶片正面上或从晶片正面去除导电材料 通过将电接触和晶片正面推动到彼此靠近来接触阳极区域外部。 在阳极和电接触之间施加电势，并且晶片相对于阳极和电触点移动。 因此允许在整个晶片正面侧面上进行全面电镀或电解抛光。

公开(公告)号：US09634412B2

公开(公告)日：2017-04-25

申请号：US13183920

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Craig Mitchell

IPC: H05K1/09 ,  H01R13/03 ,  H05K3/40 ,  H05K3/28

CPC classification number: H01R13/03 ,  H05K1/09 ,  H05K3/282 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/09745 ,  Y10T29/49155

Abstract: Electrical contacts comprising a surface with a plurality of cavities therein and their methods of manufacture and use.