公开(公告)号：US08922180B2

公开(公告)日：2014-12-30

申请号：US13800511

申请日：2013-03-13

Applicant: DORA S.p.A.

Inventor： Domenico Attianese ,  Giorgio Oddone

IPC: G05F1/00 ,  G05F1/46 ,  H02M3/158 ,  H02M1/00

CPC classification number: G05F1/46 ,  H02M3/158 ,  H02M2001/0006 ,  H02M2001/0032 ,  Y02B70/16

Abstract: Powering the internal circuitry, that is the controller of the power switch of a step-down DC-DC converter for a broad range of values of output voltage and achieving an enhanced energy saving in a low load conditions of operation is made possible by a method and implementing circuit based on defining two distinct thresholds of discrimination of the output voltage, both tied to a reference voltage, for generating two respective control signals and defining, from logical combinations of said two control signals, three distinct regions of operation of the converter upon the varying of electrical parameters, respectively identified by logical combinations of a pair of enabling signals.

Abstract translation: 为内部电路供电，即降压式DC-DC转换器的电源开关的控制器可以实现宽范围的输出电压值，并通过一种方法在低负载条件下实现增强的节能。 以及实现电路，其基于定义两个不同的输出电压鉴别阈值，两者都与参考电压相关，用于产生两个相应的控制信号，并且从所述两个控制信号的逻辑组合定义转换器的三个不同的操作区域 分别由一对使能信号的逻辑组合识别的电参数的变化。

公开(公告)号：US20130285634A1

公开(公告)日：2013-10-31

申请号：US13871809

申请日：2013-04-26

Applicant: DORA S.P.A.

Inventor： Alberto Bianco

IPC: H02M3/157

CPC classification number: H02M3/158 ,  H02M1/08 ,  H02M3/1563 ,  H02M3/157 ,  H02M2001/0025

Abstract: A control circuit for a switching voltage regulator is configured to receive an error signal representative of a regulator output voltage in relation to a nominal output voltage, and includes a set/reset flip-flop, a hysteresis comparator and a logic circuit. The flip-flop is configured to produce a switching control signal according to logic values at its set and reset terminals. The comparator is configured to produce a set signal at the set terminal when an error signal drops below a first value, and a reset signal when the error signal rises above a second value. The logic circuit is configured to prevent transmission of the reset signal to the reset terminal during a selected minimum time period and to thereafter enable transmission of the reset signal, and further, to produce an alternate reset signal at the reset terminal at the end of the selected maximum time period.

Abstract translation: 用于开关稳压器的控制电路被配置为接收代表与额定输出电压相关的调节器输出电压的误差信号，并且包括设置/复位触发器，迟滞比较器和逻辑电路。 触发器被配置为根据其设置和复位端子处的逻辑值产生开关控制信号。 比较器被配置为当误差信号低于第一值时在设定端产生设置信号，当误差信号上升到第二值以上时，产生复位信号。 逻辑电路被配置为在所选择的最小时间段期间防止复位信号传输到复位端，并且此后能够传输复位信号，并且进一步在复位端产生替代复位信号 选定的最大时间段。

公开(公告)号：US09431912B2

公开(公告)日：2016-08-30

申请号：US14456908

申请日：2014-08-11

Applicant: DORA S.p.A.

Inventor： Alberto Iorio ,  Jeanpierre Vicquery

IPC: H02M1/08 ,  H02M3/335 ,  H03K17/0412 ,  H03K17/16 ,  H03K17/13 ,  H03K17/30 ,  H02M7/217

CPC classification number: H02M3/33507 ,  H03K17/04123 ,  H03K17/133 ,  H03K17/162 ,  H03K17/302 ,  H03K2017/307

Abstract: A control device controls a rectifier of a switching converter that is supplied with an input voltage and provides an output current. The rectifier is configured to rectify the output current of the converter and has at least one transistor. The control device, when the at least one transistor is turned off, provides a slow discharge path to ground in a normal operation condition and provides a fast discharge path to ground for discharging the control terminal of the at least one transistor in response to detecting a zero cross event of the current flowing through said at least one transistor.

Abstract translation: 控制装置控制被提供有输入电压并提供输出电流的开关转换器的整流器。 整流器被配置为整流转换器的输出电流并具有至少一个晶体管。 当所述至少一个晶体管截止时，所述控制装置在正常操作状态下提供到地的缓慢放电路径，并且响应于检测到所述至少一个晶体管的控制端而向所述至少一个晶体管提供快速放电路径 流过所述至少一个晶体管的电流的零交叉事件。

公开(公告)号：US09356535B2

公开(公告)日：2016-05-31

申请号：US14458078

申请日：2014-08-12

Applicant: DORA S.p.A. ,  STMicroelectronics S.r.l.

Inventor： Alberto Iorio ,  Giuseppe Scappatura ,  Alberto Bianco ,  Claudio Adragna ,  Silvio De Simone ,  Maurizio Foresta

IPC: H02M7/217 ,  H02M3/335 ,  H02M1/00

CPC classification number: H02M7/217 ,  H02M3/33507 ,  H02M3/33592 ,  H02M2001/0058 ,  Y02B70/1475 ,  Y02B70/1491

Abstract: A control device for a transistor of a switching converter rectifier generates a control signal of the transistor and includes a circuit to measure the conduction time of the body diode of the transistor cycle by cycle. When the conduction time is greater than a first threshold, the off time instant of the transistor is delayed by a first quantity in the next cycles, until the conduction time is less than the first threshold and greater than a second threshold. When the conduction time is between the first and second thresholds, the off time instant is delayed by a fixed second quantity in the next cycles until the conduction time is lower than the second threshold, with the second quantity less than the first quantity. When the conduction time is lower than the second threshold, the off time instant is advanced by the second quantity in the next cycle.

Abstract translation: 用于开关转换器整流器的晶体管的控制装置产生晶体管的控制信号，并且包括用于逐周期地测量晶体管体二极管的导通时间的电路。 当导通时间大于第一阈值时，晶体管的截止时间瞬间在下一个周期中延迟第一量，直到导通时间小于第一阈值并大于第二阈值。 当导通时间在第一阈值和第二阈值之间时，关闭时刻在下一个周期中延迟固定的第二数量，直到导通时间低于第二阈值，第二数量小于第一数量。 当导通时间低于第二阈值时，关闭时刻在下一个周期中提前第二个数量。

公开(公告)号：US20150002109A1

公开(公告)日：2015-01-01

申请号：US14321600

申请日：2014-07-01

Applicant: DORA S.p.A.

Inventor： Alberto Bianco

IPC: H02M1/42

CPC classification number: H02M1/4225 ,  H02M1/4208 ,  Y02B70/126

Abstract: A transition mode power factor correction converter comprising a boost inductor, a switch, a diode, and output tank capacitor, has circuit means of limitation of the off-time interval of the switch to a fraction of the off-time interval, “complementary” to the on-time interval that is normally controlled for regulating the output voltage, during part of a cycle of a rectified sinusoidal voltage waveform input to the converter, when the current flowing in the inductor reaches a maximum threshold, causing the mode of operation of the device to switch from transition mode to continuous current mode for a middle phase angle region of a rectified sinusoidal input voltage waveform, under high load conditions, defined by said maximum current threshold. Current peaks amplitude and ripple are effectively reduced for same output power.

Abstract translation: 包括升压电感器，开关，二极管和输出电容器的过渡模式功率因数校正转换器具有将开关的截止时间间隔限制到关断时间间隔的一部分的电路装置，“互补” 在输入到转换器的整流正弦波电压波形的一部分周期期间，当电流中流过电感器的电流达到最大阈值时，通常被控制用于调节输出电压的导通时间间隔，导致操作模式 在由最大电流阈值定义的高负载条件下，整流正弦输入电压波形的中间相位角的转换模式切换到连续电流模式。 对于相同的输出功率，电流峰值幅度和纹波有效降低。

公开(公告)号：US20130194842A1

公开(公告)日：2013-08-01

申请号：US13749539

申请日：2013-01-24

Applicant: DORA S.P.A. ,  STMicroelectronics S.r.l.

Inventor： Alberto Bianco ,  Claudio Adragna

IPC: H02M3/156

CPC classification number: H02M3/156 ,  H02M1/4225 ,  H02M3/157 ,  Y02B70/126

Abstract: A control device controls a switching converter. The converter has an input alternating supply voltage, a regulated direct voltage on the output terminal, and a switch connected to an inductor. The control device controls the closing and opening time period of said switch for each cycle and receives a first input signal representative of the current flowing through one element of the converter. The control device comprises a counter configured to count a time period, a comparator configured to compare said first input signal with a second signal, digital control block configured to control the closing and opening of said switch and to activate said counter to start the counting of said time period when the said first input signal crosses said second signal, with said switch being closed. The digital control block is configured to open the switch when the counter finishes the counting of said time period.

Abstract translation: 控制装置控制开关转换器。 转换器具有输入交流电源电压，输出端子上的稳压直流电压和连接到电感器的开关。 控制装置控制每个周期的所述开关的闭合和打开时间周期，并且接收表示流过转换器的一个元件的电流的第一输入信号。 控制装置包括配置成对时间段进行计数的计数器，被配置为将所述第一输入信号与第二信号进行比较的比较器，被配置为控制所述开关的关闭和打开的数字控制块，并激活所述计数器以开始计数 所述时间段，当所述第一输入信号与所述第二信号相交时，所述开关闭合。 数字控制块被配置为当计数器完成所述时间段的计数时打开开关。

公开(公告)号：EP2270998B1

公开(公告)日：2013-09-18

申请号：EP10167642.7

申请日：2010-06-29

Applicant: Dora S.p.A. ,  STMicroelectronics Srl

Inventor： Guerrieri, Lorenzo ,  Saccani, Emile ,  Lasciandare, Alessandro ,  Lotito, Arturo ,  Bisaglia, Paola

IPC: H04B3/54

CPC classification number: H04B3/542 ,  H04B2203/542 ,  H04B2203/5466

公开(公告)号：EP2328312A1

公开(公告)日：2011-06-01

申请号：EP10192183.1

申请日：2010-11-23

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Veronesi, Daniele ,  Guerrieri, Lorenzo

IPC: H04L25/06 ,  H04L27/14

CPC classification number: H04L25/067 ,  H04L27/14

Abstract: A method of estimating the logarithmic likelihood ratio for two streams of samples of a received S-FSK modulated signal, comprises the step of estimating channel and noise parameters and the current signal-to-noise ratios, comparing these signal-to-noise ratios with the values of a discrete ordered set of values and identifying the respective pairs of consecutive values of the ordered set between which the current signal-to-noise ratios are comprised. The log-likelihood ratios are estimated using respective polynomial approximating functions defined on the current signal-to-noise ratio and on the coefficients stored in a look-up table corresponding to the pairs of consecutive values, in which these coefficients are related to the values of the natural logarithm of the modified Bessel function of the first kind of order zero in correspondence of values belonging to the discrete ordered set.

Abstract translation: 估计接收的S-FSK调制信号的两个样本流的对数似然比的方法包括估计信道和噪声参数以及当前信噪比的步骤，将这些信噪比与 值的离散有序集合的值并且识别其中包括当前信噪比之间的有序集合的相应的连续值对。 使用在当前信噪比上定义的各自的多项式近似函数和存储在与连续值对相对应的查找表中的系数来估计对数似然比，其中这些系数与值相关 对应于属于离散有序集的值的第一类零点的修正贝塞尔函数的自然对数。

公开(公告)号：EP1693960B1

公开(公告)日：2011-04-13

申请号：EP05425080.8

申请日：2005-02-18

Applicant: STMicroelectronics Srl ,  Dora S.p.A.

Inventor： Pannizzo, Ivo ,  Pulvirenti, Francesco

IPC: H03K3/0231

CPC classification number: H03K4/502 ,  H03K3/0231

公开(公告)号：EP1414011A1

公开(公告)日：2004-04-28

申请号：EP02425638.0

申请日：2002-10-22

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Domanin, Daniele ,  Gariboldi, Roberto ,  Ilardo, Santo

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3622 ,  G09G2310/0213 ,  G09G2330/021

Abstract: The present invention refers to a method for scanning sequence selection for displays.
In one embodiment of the method for scanning sequence selection for displays having a plurality of rows and columns, said plurality of rows and columns cross each other defining a plurality of optical elements having a first optical state and a second optical state in response to a first electric state and to a second electric state. The method comprises the phases of driving said plurality of row of said display according to a prefixed scanning ordering. The method is characterized in that said prefixed scanning ordering is predisposed by ordering every column of said plurality of column so that the total switching number between said first electric state and said second electric state is minimized.

Abstract translation: 预定义扫描排序通过对显示器的每一列进行排序而使电气状态之间的总切换次数最小化。