公开(公告)号：EP1414011A1

公开(公告)日：2004-04-28

申请号：EP02425638.0

申请日：2002-10-22

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Domanin, Daniele ,  Gariboldi, Roberto ,  Ilardo, Santo

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3622 ,  G09G2310/0213 ,  G09G2330/021

Abstract: The present invention refers to a method for scanning sequence selection for displays.
In one embodiment of the method for scanning sequence selection for displays having a plurality of rows and columns, said plurality of rows and columns cross each other defining a plurality of optical elements having a first optical state and a second optical state in response to a first electric state and to a second electric state. The method comprises the phases of driving said plurality of row of said display according to a prefixed scanning ordering. The method is characterized in that said prefixed scanning ordering is predisposed by ordering every column of said plurality of column so that the total switching number between said first electric state and said second electric state is minimized.

Abstract translation: 预定义扫描排序通过对显示器的每一列进行排序而使电气状态之间的总切换次数最小化。

公开(公告)号：EP1341150A1

公开(公告)日：2003-09-03

申请号：EP02425109.2

申请日：2002-02-28

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Rodeschini, Luca ,  Sala, Leonardo ,  Gariboldi, Roberto

IPC: G09G3/36

CPC classification number: G09G3/3625 ,  G09G3/2014 ,  G09G3/3622 ,  G09G2330/021

Abstract: Herein described is a driving method for LCD modules having a multiplicity of display elements placed in the intersections of a matrix having a plurality of row electrodes and a plurality of column electrodes. The method comprises a first phase for scanning all the row electrodes of said matrix in an interval of scanning time (NT). The first phase comprises a second phase comprising the generation of a first signal suited to energizing at least one row electrode of the matrix for a first preset interval of time (T), the generation of second signals (C3(t), C5(t)) suited to energizing respectively each column electrode of said matrix simultaneously with the energizing of at least one row electrode. The second signals (C3(t), C5(t)) are suited to determining the grey level of each display element of at least one row electrode energized by means of an alternance of corresponding values distinct signal levels (Von, Voff, V1-V3) for intervals of time (T1on, T1off) comprised in the first preset interval of time (T) by means of a first PWM modulation. The first preset interval of time (T) is lower than the interval of scanning time (NT). The first phase comprises a third phase successive to the second phase and comprising the generation of another first signal suited to energizing at least another row electrode of said matrix for a second preset period of time (T) equal and successive to the first preset interval of time, the generation of third signals (C3(t), C5(t)) suited to energizing each column electrode of the matrix simultaneously to said at least another row electrode; the third signals are suited to determining the grey level of each display element of at least another row electrode energized by means of an altemance of values corresponding to said distinct signal levels (Von, Voff, V1-V3) for intervals of time (T2on, T2off) comprised in said second preset interval of time (T) by means of a second PWM modulation. The second PWM modulation is such to ensure the continuity of the signal level of said second signals (C3(t), C5(t)) and third signals (C3(t), C5(t)) in the passage from the first preset period of time (T) to the second preset period of time (T). (Figure 5).

Abstract translation: 快来描述的是一种用于驱动具有在具有电极行的多个部分并加以电极柱的多个A矩阵的交叉点放置显示元件的多个液晶显示模块的方法。 该方法包括在扫描时间（NT）间隔扫描电极与上述矩阵的所有行中的第一阶段。 所述第一相包含第二相，其包括适合于激励所述矩阵的至少一个行电极对的时间（T）的第一预设间隔的第一信号的产生，第二信号（C 3（t）的，C5（T的产生 ））适合于分别与至少一个行电极的通电同时激励所述矩阵的每一列电极。 第二信号（C 3（t）的，C5（t））的适合于所确定的采矿由对应值的alternance手段通电的至少一个行电极的每个显示元件的灰度级不同信号电平（从，V关闭，V1 V3）为在时间（T）由第一PWM调制手段的第一预设间隔由时间（T1ON，T1off）区间。 时间的第一预设时间间隔（T）比的扫描时间（NT）的时间间隔低。 所述第一相包含第三相连续的第二相和包含至少适合于激励所述矩阵的另一行电极的时间（T）相等，并且连续到的所述第一预定间隔的第二预设时间段的另一第一信号的生成 时间，（C 3（t）的，C5（t））的适合于同时激励所述矩阵的每一列电极到所述至少另一行电极产生第三信号的; 第三信号适合于所确定的采矿由对应于所述不同信号电平值的altemance手段（通电至少另一行电极的每个显示元件的灰度级（从，V关闭，V1-V3），用于时间T2ON的间隔， T2off）由第二PWM调制的机构，在上述由时间（T）的第二预设时间间隔。 第二PWM调制正在寻求确保的信号电平的连续性，所述第二信号（C3（t）的，C5（t））和第三信号（C3（t）的，C5（T））在从所述第一预设通道 的时间周期（T）时间的第二预设时间段（T）。 （图5）。

公开(公告)号：EP1324304A1

公开(公告)日：2003-07-02

申请号：EP01830810.6

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G3/3622 ,  G09G2330/023

Abstract: The present invention refers to a supply system of the driving voltage generator of the rows and of the columns of a liquid crystal display. The supply system comprises first and second generator circuits (D3,D4) which output respective prefixed voltages (V3,V4). Each generator circuit receives two supply voltages. The first generator receives, via one voltage supply terminal, a first voltage (VLCD). The second generator receives, via one voltage supply terminal, a second voltage (GND). The other supply terminals of the generators are each connected to a charge storage device (CTNK), e.g. a capacitor, which acts as a charging tank. Charge stored in the capacitor is shared by both generators, and a control circuit (CONT) causes the voltage across the capacitor to lie within a predefined range.

Abstract translation: 本发明涉及到行的驱动电压产生器的供给系统和液晶显示器的列的。 所述供应系统包括第一和第二发生器电路（D3，D4）哪个输出respectivement前缀电压（V3，V4）。 每个发生器电路接收两个电源电压。 第一发生器接收，经由一个电压提供端，第一电压（VLCD）。 第二生成器接收，经由一个电压源端，第二电压（GND）。 发电机的另一电源端子分别连接到电荷存储装置（CTNK），例如 电容器，其用作一个充电罐。 存储在电容器的电荷被两个发生器共享;以及控制电路（CONT）使电容器两端的电压，使之处于预定范围内。

公开(公告)号：EP1583070A1

公开(公告)日：2005-10-05

申请号：EP04425227.8

申请日：2004-03-30

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Bagarelli, Fulvio ,  Gariboldi, Roberto

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3696 ,  G09G3/2011 ,  G09G3/3648 ,  G09G2310/027 ,  G09G2320/0219 ,  G09G2320/0276 ,  G09G2320/0673

Abstract: Described is a method for designing a structure for driving display devices.
In one embodiment the method for designing a structure for driving display devices comprises the steps of: considering the transmittance characteristics in relation to the voltage applied to a plurality of liquid crystal displays; defining a transmittance curve on the basis of the voltage applied to said liquid crystals, for each liquid crystal display of said plurality; applying a gamma correction, with different values of the gamma exponent, to each previously defined curve; applying a kickback correction to each previously defined curve; positioning a plurality of branch points along said curves; determining a resisitance value for each branch point and for each of said one curve for each display; choosing the value of minimum resistance for each branch point; choosing the value of maximum resistance per each branch point; calculating the difference between said value of minimum resistance for each branch point and said value of maximum resistance for each branch point; defining for each branch point a value of fixed resistance equal to said value of minimum resistance; defining for each branch point an interval of values for a variable resistance equal to said difference.

Abstract translation: 的方法创建的显示装置driverby步骤，包括：考虑到在关系的透射率特性的电压施加到多个液晶显示装置; 基于施加到所述显示器，每个显示器的电压的限定透射率曲线; 施加伽马校正，与伽马指数的不同的值，每个透射率曲线; 施加反冲校正每条曲线; 沿着所述曲线定位分支点; 确定性采矿每个分支点和用于为每个显示每条曲线的电阻值; 选择用于每个分支点的最小电阻值; 选择的每个分支点处的最大电阻值; 计算所述最低电阻值和每个分支点所述最大电阻值之间的差; - 定义为每个分支点处的固定电阻值等于所述最小电阻值; - 定义为值的间隔为等于所述差的可变电阻的每个分支点。

公开(公告)号：EP1365384A1

公开(公告)日：2003-11-26

申请号：EP02425326.2

申请日：2002-05-23

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Domanin, Daniele ,  Gariboldi, Roberto

IPC: G09G3/36

CPC classification number: G09G3/3625 ,  G09G3/2018 ,  G09G3/2022 ,  G09G2320/0247 ,  G09G2320/0266

Abstract: The present invention relates to a driving method for flat panel display devices, particularly a driving method combining a Multi Line Addressing (MLA) technique and a Frame Rate Control (FRC) technique, for flat panel display devices such as Liquid Crystal Display (LCD).
In an embodiment the method of driving an image display device comprises the following steps: dividing row electrodes of an image device, having a plurality of row electrodes and a plurality of column electrodes, into a plurality of subgroups; selecting one of the plurality of said subgroups having a prefixed number of electrodes; performing a grey scale display by a frame rate control (FRC) by using a prefixed number of frames and a prefixed number of bits representing the grey levels; decomposing one of said frame in a number of time instants proportional to said prefixed number of electrodes; putting the bits representing the grey levels equally distributed in said prefixed number of frames.

Abstract translation: 本发明涉及用于平板显示装置的驱动方法，特别是组合多行寻址（MLA）技术和帧速率控制（FRC）技术的驱动方法，用于诸如液晶显示器（LCD）的平板显示装置， 。 在一个实施例中，驱动图像显示装置的方法包括以下步骤：将具有多个行电极和多个列电极的图像装置的行电极分成多个子组; 选择所述多个所述子组中的一个具有预定数量的电极; 通过使用预定数量的帧和表示灰度级的前缀位数来执行帧速率控制（FRC）的灰度级显示; 在与所述预定数量的电极成比例的多个时刻中分解所述帧中的一个; 将表示灰度级的位平均分配在所述前缀数目的帧中。

公开(公告)号：EP0735677B1

公开(公告)日：1999-12-22

申请号：EP95830123.6

申请日：1995-03-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  STMicroelectronics S.r.l.

Inventor： Pulvirenti, Francesco ,  Ursino, Riccardo ,  Gariboldi, Roberto

IPC: H03K3/011 ,  H03K3/0231

CPC classification number: H03K3/011 ,  H03K3/0231 ,  H03K3/354

公开(公告)号：EP0909030A1

公开(公告)日：1999-04-14

申请号：EP97830506.8

申请日：1997-10-10

Applicant: STMicroelectronics S.r.l.

Inventor： Genova, Angelo ,  Gariboldi, Roberto ,  Cantone, Giuseppe

IPC: H03K3/0232 ,  H03K3/355

CPC classification number: H03K3/011 ,  H03K3/0232 ,  H03K3/355

Abstract: Integrated device (202) for use in a monostable circuit (200), the integrated device (202) having a programming terminal (103) able to be linked to external resistive means (Rext) so as to programme the duration of a non-stable state of the circuit (200) and comprising a comparator (120) having a first (+) and a second (-) input terminal and an output terminal for generating an output signal (Vout) of the circuit (200), capacitive means (C) linked to the first input terminal (+) of the comparator (120) so as to apply thereto a voltage (Vc) correlated with the voltage on the capacitive means (C), control means (SW,115) linked to the first input terminal (+) of the comparator (120) so as to switch the circuit (200) to the non-stable state, and means (M1, M2) for sending a current (Iref1) which passes through the resistive means (Rext) to the capacitive means (C), in which the programming terminal (103) is linked to the second input terminal (-) of the comparator (120) so as to apply thereto a voltage (Vref1) correlated with the voltage on the resistive means (Rext).

Abstract translation: 用于单稳态电路（200）的集成器件（202），该集成器件（202）具有能够连接到外部电阻器件（Rext）的编程端子（103），以便编程不稳定的持续时间 电路（200）的状态，并且包括具有第一（+）和第二（ - ）输入端子的比较器（120）和用于产生电路（200）的输出信号（Vout）的输出端子，电容装置 C）连接到比较器（120）的第一输入端（+），以便向其施加与电容装置（C）上的电压相关的电压（Vc）;与第一输入端连接的控制装置（SW，115） （120）的输入端（+），将电路（200）切换到非稳定状态;以及用于发送通过电阻装置（Rext）的电流（Iref1）的装置（M1，M2） 到电容装置（C），其中编程端子（103）连接到比较器（120）的第二输入端子（ - ），以便施加 到与电阻装置（Rext）上的电压相关的电压（Vref1）。

公开(公告)号：EP0887931A1

公开(公告)日：1998-12-30

申请号：EP97830296.6

申请日：1997-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Tarantola, Mario ,  Cantone, Giuseppe ,  Genova, Angelo ,  Gariboldi, Roberto

IPC: H03K17/06

CPC classification number: H03K17/08122 ,  H03K17/063

Abstract: A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap (Cp) capacitor charged by a diode (D1) connected to the supply node (Vs) of the circuit, by an (IO1) inverter driven by a logic control circuit in function of a first Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase where the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, comprises further a second inverter (M1, M2), functionally referred to the charging node of said bootstrap (Cp) capacitor and to the voltage of the output node (A) of said inverter (IO1) and having an input coupled to said second logic signal (UVLOb) and an output coupled to the gate node of said LDMOS transistor (LD), for preventing accidental undue switch-on of the LDMOS transistor.

Abstract translation: 一种用于通过用作源极跟随器级的LDMOS集成晶体管（LD）对电容（C）进行充电的电路，以通过经由自举（Cp）电容器充电的自举（Cp）电容器模拟电容的高电压充电二极管的方式被控制 和由第一低栅极驱动信号的逻辑控制电路驱动的（IO1）反相器和第二逻辑信号（UVLOb）连接的电路的供电节点（Vs）的二极管（D1） 在电源电压（Vs）低于集成电路的最小接通电压的阶段中，还包括在功能上称为所述自举（Cp）电容器的充电节点的第二反相器（M1，M2），并且 所述反相器（IO1）的输出节点（A）的电压和耦合到所述第二逻辑信号（UVLOb）的输入端和耦合到所述LDMOS晶体管（LD）的栅极节点的输出端，用于防止意外不适当的开关 - 在LDMOS晶体管上。

公开(公告)号：EP0810504B1

公开(公告)日：2002-09-18

申请号：EP96830312.3

申请日：1996-05-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  STMicroelectronics S.r.l.

Inventor： Ursino, Riccardo ,  Gariboldi, Roberto

IPC: G05F1/00 ,  G05F1/575

CPC classification number: G05F1/575

公开(公告)号：EP0733959B1

公开(公告)日：2001-06-13

申请号：EP95830111.1

申请日：1995-03-24

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  STMicroelectronics S.r.l.

Inventor： Gariboldi, Roberto ,  Pulvirenti, Francesco

IPC: G05F3/26 ,  G05F3/28

CPC classification number: G11C5/147 ,  G05F1/465 ,  G05F3/267