公开(公告)号：WO2006049780A8

公开(公告)日：2007-04-26

申请号：PCT/US2005035466

申请日：2005-09-30

Applicant: FREESCALE SEMICONDUCTOR INC ,  LIEN MITCHELL T ,  DURLAM MARK A ,  MEIXNER THOMAS V ,  WISE LOREN J

Inventor： LIEN MITCHELL T ,  DURLAM MARK A ,  MEIXNER THOMAS V ,  WISE LOREN J

IPC: H01L21/00

CPC classification number: H01L43/12 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76843

Abstract: Magnetoelectric memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line (26) disposed at least partially within a dielectric layer (24). The dielectic material layer overlies an interconnect stack. A conductive barrier layer (40, 42) having a first portion (40) and a second portion (42) id deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer (46) is formed overlying the first portion and an electrode layer (48) is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

Abstract translation: 提供了使用阻挡层作为材料去除停止层的这种结构的磁电存储元件结构和方法。 所述方法包括形成至少部分地设置在电介质层（24）内的数字线（26）。 介电材料层覆盖互连叠层。 具有沉积有第一部分（40）和第二部分（42）的导电阻挡层（40,42）。 第一部分覆盖数字线，第二部分设置在空隙空间内并与互连叠层电连通。 存储元件层（46）形成在第一部分上方，并且沉积在存储元件层上的电极层（48）。 然后对电极层和存储元件层进行图案化和蚀刻。

公开(公告)号：WO2007040991A2

公开(公告)日：2007-04-12

申请号：PCT/US2006/036634

申请日：2006-09-20

Applicant: FREESCALE SEMICONDUCTOR INC. ,  CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A.

Inventor： CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A.

IPC: H01L21/00 ,  H01L21/336

CPC classification number: H01L27/228 ,  G01K7/36 ,  Y10T428/1114

Abstract: Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit (600) are provided. According to one exemplary method, a Magnetic Tunnel Junction ("MTJ") temperature sensor (608) is provided over the heat source (604). The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.

Abstract translation: 提供了感测设置在集成电路（600）的基板中的热源的温度的技术。 根据一个示例性方法，在热源（604）之上提供磁隧道结（“MTJ”）温度传感器（608）。 MTJ温度传感器包括被配置为在其操作期间输出电流的MTJ内核。 电流值根据特定MTJ磁芯的电阻值而变化。 MTJ芯的电阻值随着热源的温度而变化。 然后，MTJ芯的电流的值可以与热源的相应温度相关联。

公开(公告)号：WO2007027381A1

公开(公告)日：2007-03-08

申请号：PCT/US2006/030817

申请日：2006-08-08

Applicant: FREESCALE SEMICONDUCTOR ,  CHUNG, Young, Sir ,  BAIRd, Robert, W. ,  DURLAM, Mark, A. ,  GRYNKEWICH, Gregory, W. ,  SALTER, Eric, J.

Inventor： CHUNG, Young, Sir ,  BAIRd, Robert, W. ,  DURLAM, Mark, A. ,  GRYNKEWICH, Gregory, W. ,  SALTER, Eric, J.

IPC: H01L29/82

CPC classification number: H01L27/228

Abstract: An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

Abstract translation: 集成电路器件（300）包括形成在衬底（308）上的衬底（301）和MRAM架构（314）。 MRAM架构（314）包括形成在基板（301）上的MRAM电路（318）。 和耦合到并形成在MRAM电路（318）上方的MRAM单元（316）。 另外，与MRAM单元（316）结合形成无源器件（320）。 无源器件（320）可以是一个或多个电阻器和一个或多个电容器。 MRAM架构（314）和无源器件（320）的并行制造有助于在衬底（404,504）的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

公开(公告)号：WO2004095515A2

公开(公告)日：2004-11-04

申请号：PCT/US2004/011872

申请日：2004-04-16

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  WILLIAMS, Richard ,  GRYNKEWICH, Gregory, W. ,  BUTCHER, Brian, R. ,  DURLAM, Mark, A. ,  KYLER, Kelly ,  SNYDER, Charles, A. ,  SMITH, Kenneth, H. ,  TRACY, Clarence, J.

Inventor： GRYNKEWICH, Gregory, W. ,  BUTCHER, Brian, R. ,  DURLAM, Mark, A. ,  KYLER, Kelly ,  SNYDER, Charles, A. ,  SMITH, Kenneth, H. ,  TRACY, Clarence, J.

IPC: H01L

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer (26) is deposited overlying the memory element layer (18). A first dielectric layer (28) is deposited overlying the first electrically conductive layer (26) and is patterned and etched to form a first masking layer (28). Using the first masking layer (28), the first electrically conductive layer (26) is etched. A second dielectric layer (36) is deposited overlying the first masking layer (28) and the dielectric region. A portion of the second dielectric layer (36) is removed to expose the first masking layer (28). The second dielectric layer (36) and the first masking layer (28) are subjected to an etching chemistry such that the first masking layer (28) is etched at a faster rate than the second dielectric layer (36). The etching exposes the first electrically conductive layer (26).

Abstract translation: 用于使覆盖磁电元件的导电层接触的方法包括形成覆盖在电介质区域上的存储元件层。 沉积在存储元件层（18）上的第一导电层（26）。 沉积覆盖在第一导电层（26）上的第一介电层（28）并被图案化和蚀刻以形成第一掩模层（28）。 使用第一掩模层（28），蚀刻第一导电层（26）。 沉积在第一掩模层（28）和电介质区域上的第二介电层（36）。 去除第二介电层（36）的一部分以露出第一掩模层（28）。 对第二介电层（36）和第一掩模层（28）进行蚀刻化学处理，使得以比第二介电层（36）更快的速率蚀刻第一掩模层（28）。 蚀刻暴露第一导电层（26）。