公开(公告)号：WO2007040991A3

公开(公告)日：2009-04-16

申请号：PCT/US2006036634

申请日：2006-09-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A

Inventor： CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A

IPC: H01L21/00

CPC classification number: H01L27/228 ,  G01K7/36 ,  Y10T428/1114

Abstract: Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit (600) are provided. According to one exemplary method, a Magnetic Tunnel Junction ("MTJ") temperature sensor (608) is provided over the heat source (604). The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.

Abstract translation: 提供了感测设置在集成电路（600）的基板中的热源的温度的技术。 根据一个示例性方法，在热源（604）之上提供磁隧道结（“MTJ”）温度传感器（608）。 MTJ温度传感器包括被配置为在其操作期间输出电流的MTJ内核。 电流值根据特定MTJ磁芯的电阻值而变化。 MTJ芯的电阻值随着热源的温度而变化。 然后，MTJ芯的电流的值可以与热源的相应温度相关联。

公开(公告)号：WO2007005303A2

公开(公告)日：2007-01-11

申请号：PCT/US2006024228

申请日：2006-06-22

Applicant: FREESCALE SEMICONDUCTOR INC ,  GRYNKEWICH GREGORY W ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A ,  SALTER ERIC J

Inventor： GRYNKEWICH GREGORY W ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A ,  SALTER ERIC J

IPC: G11C11/14

CPC classification number: G11C11/1659 ,  H01F10/3254

Abstract: An integrated circuit device (300) includes a magnetic random access memory ("MRAM") architecture and a smart power integrated circuit architecture formed on the same substrate (302) using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component (304), a digital logic component (306), and an analog control component (312) formed by the front end process, and a sensor architecture (308) formed by the back end process. The MRAM architecture (310) includes an MRAM circuit component (314) formed by the front end process and an MRAM cell array (310) formed by the back end process. In one practical embodiment, the sensor architecture (308) includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array (316). The concurrent fabrication of the MRAM architecture (310) and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

Abstract translation: 集成电路器件（300）包括磁性随机存取存储器（“MRAM”）结构和使用相同制造工艺技术在相同衬底（302）上形成的智能功率集成电路架构。 制造工艺技术是具有前端工艺和后端工艺的模块化工艺。 在该示例实施例中，智能电力架构包括由前端处理形成的电源电路部件（304），数字逻辑部件（306）和模拟控制部件（312），以及传感器架构（308），由 后端进程。 MRAM架构（310）包括由前端处理形成的MRAM电路部件（314）和由后端处理形成的MRAM单元阵列（310）。 在一个实际的实施例中，传感器架构（308）包括由MRAM单元阵列（316）使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构（310）和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效且成本有效的使用，导致三维集成。

公开(公告)号：WO2006049780A3

公开(公告)日：2006-05-11

申请号：PCT/US2005/035466

申请日：2005-09-30

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  LIEN, Mitchell, T. ,  DURLAM, Mark, A. ,  MEIXNER, Thomas, V. ,  WISE, Loren, J.

Inventor： LIEN, Mitchell, T. ,  DURLAM, Mark, A. ,  MEIXNER, Thomas, V. ,  WISE, Loren, J.

IPC: H01L21/00

Abstract: Magnetoelectric memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line (26) disposed at least partially within a dielectric layer (24). The dielectic material layer overlies an interconnect stack. A conductive barrier layer (40, 42) having a first portion (40) and a second portion (42) id deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer (46) is formed overlying the first portion and an electrode layer (48) is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

公开(公告)号：WO2007053341A3

公开(公告)日：2007-11-15

申请号：PCT/US2006041148

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A

Inventor： CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A

IPC: G11C11/14

CPC classification number: H01L43/12 ,  H01L27/228

Abstract: An integrated circuit device (800) is provided which comprises a substrate (801), a conductive line (807) configured to experience a pressure, and a magnetic tunnel junction ("MTJ") core (802) formed between the substrate and the current line. The conductive line (807) is configured to move in response to the pressure, and carries a current which generates a magnetic field. The MTJ core (802) has a resistance value which varies based on the magnetic field. The resistance of the MTJ core (802) therefore varies with respect to changes in the pressure. The MTJ core (802) is configured to produce an electrical output signal which varies as a function of the pressure.

Abstract translation: 提供了一种集成电路器件（800），其包括衬底（801），被配置为经受压力的导线（807）和形成在衬底和电流之间的磁性隧道结（“MTJ”）芯 线。 导线807配置为响应于压力移动，并且传送产生磁场的电流。 MTJ磁芯（802）具有基于磁场而变化的电阻值。 因此，MTJ芯（802）的电阻因压力变化而变化。 MTJ内核（802）被配置为产生作为压力的函数而变化的电输出信号。

公开(公告)号：WO2007053340A3

公开(公告)日：2007-05-10

申请号：PCT/US2006/041147

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR INC. ,  CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A. ,  GRYNKEWICH, Gregory W. ,  SALTER, Eric J. ,  ZUO, Jiang-Kai

Inventor： CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A. ,  GRYNKEWICH, Gregory W. ,  SALTER, Eric J. ,  ZUO, Jiang-Kai

IPC: G11C11/00

Abstract: An integrated circuit device (600) is provided which includes an active circuit component (604, 804) and a current sensor (602, 802). The active circuit component (604, 804) may be coupled between a first conductive layer (206) and a second conductive layer (210), and is configured to produce a first current. The current sensor (602, 802) is disposed over the active circuit component. The current sensor (602, 802) may comprise a Magnetic Tunnel Junction ("MTJ") core disposed between the first conductive layer (206) and the second conductive layer (210). The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

公开(公告)号：WO2006049780A2

公开(公告)日：2006-05-11

申请号：PCT/US2005035466

申请日：2005-09-30

Applicant: FREESCALE SEMICONDUCTOR INC ,  LIEN MITCHELL T ,  DURLAM MARK A ,  MEIXNER THOMAS V ,  WISE LOREN J

Inventor： LIEN MITCHELL T ,  DURLAM MARK A ,  MEIXNER THOMAS V ,  WISE LOREN J

IPC: H01L21/00

CPC classification number: H01L43/12 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76843

Abstract: Magnetoelectric memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line (26) disposed at least partially within a dielectric layer (24). The dielectic material layer overlies an interconnect stack. A conductive barrier layer (40, 42) having a first portion (40) and a second portion (42) id deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer (46) is formed overlying the first portion and an electrode layer (48) is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

Abstract translation: 提供了使用阻挡层作为材料去除停止层的这种结构的磁电存储元件结构和方法。 所述方法包括形成至少部分地设置在电介质层（24）内的数字线（26）。 介电材料层覆盖互连叠层。 具有沉积有第一部分（40）和第二部分（42）的导电阻挡层（40,42）。 第一部分覆盖数字线，第二部分设置在空隙空间内并与互连叠层电连通。 存储元件层（46）形成在第一部分上方，并且沉积在存储元件层上的电极层（48）。 然后对电极层和存储元件层进行图案化和蚀刻。

公开(公告)号：WO2004095459A3

公开(公告)日：2005-03-24

申请号：PCT/US2004011864

申请日：2004-04-16

Applicant: FREESCALE SEMICONDUCTOR INC ,  GRYNKEWICH GREGORY ,  DEHERRERA MARK ,  DURLAM MARK A ,  TRACY CLARENCE J

Inventor： GRYNKEWICH GREGORY ,  DEHERRERA MARK ,  DURLAM MARK A ,  TRACY CLARENCE J

IPC: G11C20060101 ,  G11C8/02 ,  H01L21/00 ,  H01L21/8246 ,  H01L27/22 ,  H01L29/00 ,  H01L29/82

CPC classification number: H01L27/228 ,  B82Y10/00

Abstract: A method for fabricating an MRAM device structure (10) includes providing a substrate (12) on which is formed a first transistor (14) and a second transistor (14). An operative memory element device (60) is formed in electrical contact with the first transistor (14). At least a portion of a false memory element device (58) is formed in electrical contact with the second transistor (14). A first dielectric layer (62) is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via (66) to the at least a portion of a false memory element device (58) and a second via (64) to the operative memory element device (60). An electrically conductive interconnect layer (68) is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device (58) to the operative memory element device (64).

Abstract translation: 一种用于制造MRAM器件结构（10）的方法包括提供其上形成有第一晶体管（14）和第二晶体管（14）的衬底（12）。 操作存储元件装置（60）形成为与第一晶体管（14）电接触。 伪存储元件器件（58）的至少一部分形成为与第二晶体管（14）电接触。 第一介电层（62）沉积在伪存储元件装置和操作存储元件装置的至少一部分上。 第一介电层被蚀刻以同时形成第一通孔（66）到伪存储元件器件（58）的至少一部分和第二通孔（64）到操作存储元件器件（60）。 沉积导电互连层（68），使得导电互连层从假存储元件装置（58）的至少一部分延伸到可操作存储元件装置（64）。

公开(公告)号：WO2007053340A2

公开(公告)日：2007-05-10

申请号：PCT/US2006041147

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A ,  GRYNKEWICH GREGORY W ,  SALTER ERIC J ,  ZUO JIANG-KAI

Inventor： CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A ,  GRYNKEWICH GREGORY W ,  SALTER ERIC J ,  ZUO JIANG-KAI

IPC: G11C11/00

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

Abstract: An integrated circuit device (600) is provided which includes an active circuit component (604, 804) and a current sensor (602, 802). The active circuit component (604, 804) may be coupled between a first conductive layer (206) and a second conductive layer (210), and is configured to produce a first current. The current sensor (602, 802) is disposed over the active circuit component. The current sensor (602, 802) may comprise a Magnetic Tunnel Junction ("MTJ") core disposed between the first conductive layer (206) and the second conductive layer (210). The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

Abstract translation: 提供了一种集成电路装置（600），其包括有源电路部件（604,804）和电流传感器（602,802）。 有源电路组件（604,804）可以耦合在第一导电层（206）和第二导电层（210）之间，并且被配置为产生第一电流。 电流传感器（602,802）设置在有源电路部件上。 电流传感器（602,802）可以包括设置在第一导电层（206）和第二导电层（210）之间的磁隧道结（“MTJ”）芯。 MTJ内核被配置为基于在MTJ核心处感测到的第一电流来感测第一电流并产生第二电流。

公开(公告)号：WO2006132750A2

公开(公告)日：2006-12-14

申请号：PCT/US2006/017689

申请日：2006-05-09

Applicant: FREESCALE SEMICONDUCTOR ,  DURLAM, Mark, A. ,  CHUNG, Young, Sir ,  BAIRD, Robert, W. ,  ENGEL, Bradley, N.

Inventor： DURLAM, Mark, A. ,  CHUNG, Young, Sir ,  BAIRD, Robert, W. ,  ENGEL, Bradley, N.

IPC: H01L43/00

CPC classification number: H01L27/222 ,  G11C11/16 ,  H01F17/0006 ,  H01F19/04 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device (300) includes a magnetic random access memory ("MRAM") architecture (310) and at least one inductance element (312, 314) formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture (310) and the inductance element (312, 314) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

Abstract translation: 集成电路器件（300）包括磁性随机存取存储器（“MRAM”）架构（310）和使用相同制造工艺技术形成在同一衬底上的至少一个电感元件（312,314）。 可以是电感器或变压器的电感元件形成在与MRAM架构的程序行相同的金属层（或多层）上。 除了编程线层之外，可以将任何可用的金属层添加到电感元件中以提高其效率。 MRAM架构（310）和电感元件（312,314）的并行制造有助于在衬底的有源电路块上可用的物理空间的有效且成本有效的使用，导致三维集成。

公开(公告)号：WO2004095515A8

公开(公告)日：2005-11-17

申请号：PCT/US2004011872

申请日：2004-04-16

Applicant: FREESCALE SEMICONDUCTOR INC ,  GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J

Inventor： GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J ,  WILLIAMS RICHARD

IPC: G11C11/15 ,  H01L21/8246 ,  H01L43/12 ,  G11C8/02 ,  G11C11/00 ,  H01L43/00

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer (26) is deposited overlying the memory element layer (18). A first dielectric layer (28) is deposited overlying the first electrically conductive layer (26) and is patterned and etched to form a first masking layer (28). Using the first masking layer (28), the first electrically conductive layer (26) is etched. A second dielectric layer (36) is deposited overlying the first masking layer (28) and the dielectric region. A portion of the second dielectric layer (36) is removed to expose the first masking layer (28). The second dielectric layer (36) and the first masking layer (28) are subjected to an etching chemistry such that the first masking layer (28) is etched at a faster rate than the second dielectric layer (36). The etching exposes the first electrically conductive layer (26).

Abstract translation: 用于使覆盖磁电元件的导电层接触的方法包括形成覆盖在电介质区域上的存储元件层。 沉积在存储元件层（18）上的第一导电层（26）。 沉积覆盖在第一导电层（26）上的第一介电层（28）并被图案化和蚀刻以形成第一掩模层（28）。 使用第一掩模层（28），蚀刻第一导电层（26）。 沉积在第一掩模层（28）和电介质区域上的第二介电层（36）。 去除第二介电层（36）的一部分以露出第一掩模层（28）。 对第二介电层（36）和第一掩模层（28）进行蚀刻化学处理，使得以比第二介电层（36）更快的速率蚀刻第一掩模层（28）。 蚀刻暴露第一导电层（26）。