公开(公告)号：WO2010062360A1

公开(公告)日：2010-06-03

申请号：PCT/US2009/005901

申请日：2009-10-30

Applicant: GLOBALFOUNDRIES INC. ,  AUBEL, Oliver ,  POPPE, Jens ,  KURZ, Andreas ,  BOSCHKE, Roman

Inventor： AUBEL, Oliver ,  POPPE, Jens ,  KURZ, Andreas ,  BOSCHKE, Roman

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49107 ,  H01L2924/00

Abstract: In sophisticated integrated circuits, an electronic fuse (200) may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region (203) as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space- efficient layout of the electronic fuses may be accomplished.

Abstract translation: 在复杂的集成电路中，可以形成电子熔丝（200），使得可以通过包括增加的电流密度的至少一个区域来实现对电迁移的增加的灵敏度。 这可以通过形成作为非线性配置的对应的熔断器区域（203）来实现，其中在线性段的对应连接部分期间，在施加编程电压期间可能发生期望的增强的电流拥挤。 因此，可以实现电子保险丝的可靠性和空间效率更高的布局。

公开(公告)号：WO2010062357A1

公开(公告)日：2010-06-03

申请号：PCT/US2009/005894

申请日：2009-10-30

Applicant: GLOBALFOUNDRIES INC. ,  LEHR, Matthias ,  KUECHENMEISTER, Frank ,  SELIGER, Frank

Inventor： LEHR, Matthias ,  KUECHENMEISTER, Frank ,  SELIGER, Frank

IPC: B21C3/02 ,  B21C3/04

CPC classification number: B21C3/02 ,  B21C3/04 ,  H01L24/43 ,  H01L24/45 ,  H01L24/745 ,  H01L2224/05624 ,  H01L2224/4321 ,  H01L2224/43847 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/745 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/00015

Abstract: Bonding wires (252A) for sophisticated bonding applications may be efficiently formed on the basis of a corresponding template device (200) that may be formed on the basis of semiconductor material (201), such as silicon, in combination with associated fabrication techniques, such as lithography and etch techniques. Hence, any appropriate diameter and cross-sectional shape may be obtained with a high degree of accuracy and reliability.

Abstract translation: 可以基于可以基于诸如硅的半导体材料（201）形成的相应的模板装置（200），结合相关的制造技术，有效地形成用于复杂粘合应用的接合线（252A），例如 作为光刻和蚀刻技术。 因此，可以以高精度和可靠性获得任何适当的直径和横截面形状。

公开(公告)号：WO2010039231A1

公开(公告)日：2010-04-08

申请号：PCT/US2009/005395

申请日：2009-09-30

Applicant: GLOBALFOUNDRIES INC. ,  HOENTSCHEL, Jan ,  MULFINGER, Robert ,  GRIEBENOW, Uwe

Inventor： HOENTSCHEL, Jan ,  MULFINGER, Robert ,  GRIEBENOW, Uwe

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: In a CMOS manufacturing process flow, a cap layer (151C) formed on top of a gate electrode material (151 A) may be maintained throughout the entire implantation sequence for defining the drain and source regions (154) and may be removed during an etch process in which the width of a sidewall spacer structure (155) may be reduced so as to reduce a lateral offset of metal suicide regions (156) and of a stressed dielectric material. Thus, overall enhanced transistor performance may be obtained while nevertheless providing a high degree of compatibility with existing CMOS process strategies.

Abstract translation: 在CMOS制造工艺流程中，可以在整个注入顺序期间保持形成在栅电极材料（151A）的顶部上的覆盖层（151C），以限定漏极和源极区域（154），并且可以在蚀刻期间去除 可以减小侧壁间隔结构（155）的宽度以减少金属硅化物区域（156）和应力介电材料的横向偏移的过程。 因此，可以获得总体增强的晶体管性能，同时提供与现有CMOS工艺策略的高度兼容性。

公开(公告)号：WO2010011293A1

公开(公告)日：2010-01-28

申请号：PCT/US2009/004229

申请日：2009-07-21

Applicant: GLOBALFOUNDRIES INC. ,  YANG, Frank Bin ,  HARGROVE, Michael, J. ,  PAL, Rohit

Inventor： YANG, Frank Bin ,  HARGROVE, Michael, J. ,  PAL, Rohit

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. One exemplary method comprises providing a silicon-comprising substrate having a first surface, etching a recess into the first surface, the recess having a side surface and a bottom surface, implanting carbon ions into the side surface and the bottom surface, and forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface.

Abstract translation: 提供了用于制造半导体器件的半导体器件和方法。 一种示例性方法包括提供具有第一表面的含硅衬底，将凹陷蚀刻到第一表面中，凹部具有侧表面和底表面，将碳离子注入侧表面和底表面，并形成杂质 掺杂的覆盖在侧表面和底表面上的含硅区域。

公开(公告)号：WO2019016672A1

公开(公告)日：2019-01-24

申请号：PCT/IB2018/055243

申请日：2018-07-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED ,  GLOBALFOUNDRIES INC, ,  SAMSUNG ELECTRONICS CO, LTD,

Inventor： FAN, Su Chen ,  PRANATHARTHIHARAN, Balasubramanian ,  GREENE, Andrew ,  XIE, Ruilong ,  RAYMOND, Mark, Victor ,  LIAN, Sean

IPC: H01L21/8238

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided, in one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers In a dielectric; forming gate trenches by selectively rernoving the dielectric from: regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：WO2014105792A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/077418

申请日：2013-12-23

Applicant: INTERMOLECULAR, INC ,  GLOBALFOUNDRIES, INC

Inventor： FOSTER, John ,  METZGER, Sven

IPC: H01L21/66

CPC classification number: H01L21/32134 ,  H01L21/28088 ,  H01L21/28123 ,  H01L22/30 ,  H01L29/517 ,  H01L29/6653

Abstract: Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7 % by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40C and 60C.

Abstract translation: 提供了半导体基板的高效率组合测试方法，每个包括多个位置隔离区域。 每个位置分离区域包括氮化钛结构以及氧化铪结构和/或多晶硅结构。 每个位置分离区域暴露于包括硫酸，过氧化氢和氟化氢的蚀刻溶液。 蚀刻溶液的组成和/或蚀刻条件在位置分离区域之间变化，以研究该变化对氮化钛相对于氧化铪和/或多晶硅的蚀刻选择性的影响以及蚀刻速率。 蚀刻溶液中硫酸和/或过氧化氢的浓度可以小于7体积％，而氟化氢的浓度可以在50ppm和200ppm之间。 在一些实施例中，蚀刻溶液的温度保持在约40℃至60℃之间。

公开(公告)号：WO2011025800A3

公开(公告)日：2011-04-21

申请号：PCT/US2010046568

申请日：2010-08-25

Applicant: GLOBALFOUNDRIES INC ,  BEYER SVEN ,  CARTER RICK ,  HELLMICH ANDREAS ,  REIMER BERTHOLD

Inventor： BEYER SVEN ,  CARTER RICK ,  HELLMICH ANDREAS ,  REIMER BERTHOLD

IPC: H01L21/28

CPC classification number: H01L21/28247 ,  H01L21/0206 ,  H01L21/02244 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

Abstract: In semiconductor devices, integrity of a titanium nitride material (152) may be increased by exposing the material to an oxygen plasma (110) after forming a thin silicon nitride -based material. The oxygen plasma (110) may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes (111) based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material (152). In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.

Abstract translation: 在半导体器件中，氮化钛材料（152）的完整性可以通过在形成薄的氮化硅基材料之后将材料暴露于氧等离子体（110）而增加。 氧等离子体（110）可能导致任何微小表面部分的附加钝化，这些微小表面部分可能不被氮化硅基材料适当地覆盖。 因此，可以在附加钝化之后进行有效的清洁配方，例如基于SPM的清洁过程（111），而不会导致氮化钛材料（152）的不必要的材料损失。 以这种方式，可以在有效的清洁过程的基础上形成具有非常薄的保护衬垫材料的复杂的高k金属栅极堆叠，而不会在早期制造阶段中过度地造成显着的产量损失。

公开(公告)号：WO2011019913A1

公开(公告)日：2011-02-17

申请号：PCT/US2010/045320

申请日：2010-08-12

Applicant: GLOBALFOUNDRIES INC. ,  POTOK, Ronald, M. ,  GORUGANTHU, Rama, R. ,  BRUCE, Michael, R.

Inventor： POTOK, Ronald, M. ,  GORUGANTHU, Rama, R. ,  BRUCE, Michael, R.

IPC: H01L27/146 ,  H01L31/113

CPC classification number: H01L31/113

Abstract: [041] A silicon photon detector device and methodology are provided for detecting incident photons in a partially depleted floating body SOI field-effect transistor (310) which traps charges created by visible and mid infrared light in a floating body region (304) when the silicon photon detector is configured in a detect mode, and then measures or reads the resulting enhanced drain current with a current detector in a read mode.

Abstract translation: 提供硅光子检测器装置和方法，用于检测部分耗尽的浮体SOI场效应晶体管（310）中的入射光子，其捕获在浮体区域（304）中由可见光和中红外光产生的电荷， 硅光子检测器被配置为检测模式，然后在读取模式下用电流检测器测量或读取所得到的增强的漏极电流。

公开(公告)号：WO2011013092A1

公开(公告)日：2011-02-03

申请号：PCT/IB2010/053459

申请日：2010-07-29

Applicant: GLOBALFOUNDRIES INC. ,  KRONHOLZ, Stephan ,  LENSKI, Markus ,  RICHTER, Ralf

Inventor： KRONHOLZ, Stephan ,  LENSKI, Markus ,  RICHTER, Ralf

IPC: H01L27/28 ,  G11C13/02 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L27/281 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0003 ,  H01L51/0591

Abstract: Memory cells in integrated circuit devices may be formed on the basis of functional molecules (120) which may be positioned within via openings (111 ) on the basis of appropriate patterning techniques, which may also be used for forming semiconductor-based integrated circuits. Consequently, memory cells may be formed on a ''molecular" level without requiring extremely sophisticated patterning regimes, such as electron beam lithography and the like.

Abstract translation: 可以基于功能分子（120）形成集成电路器件中的存储器单元，该功能分子可以基于合适的图案化技术而定位在通孔开口（111）内，其也可用于形成基于半导体的集成电路。 因此，可以在“分子”级别上形成记忆单元，而不需要非常复杂的图案化方案，例如电子束光刻等。

公开(公告)号：WO2010144347A1

公开(公告)日：2010-12-16

申请号：PCT/US2010/037592

申请日：2010-06-07

Applicant: GLOBALFOUNDRIES INC. ,  ZHOU, Jingrong ,  WU, David ,  BULLER, James, F.

Inventor： ZHOU, Jingrong ,  WU, David ,  BULLER, James, F.

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L21/84 ,  H01L27/1203

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode (411) and a P+? substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain (415), through a conductive contact (451), a metal line (459), a second conductive contact (453), an SOI diode (411), isolated from the transistor (409), a third conductive contact (455), a second conductive line (461), and a fourth conductive contact (457) to a P+?-doped substrate contact (449) in the bulk silicon layer (403) of the SOI substrate.

Abstract translation: 形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。 实施例包括SOI膜二极管（411）和P + 衬底接点作为充电保护装置。 实施例还包括来自SOI晶体管漏极（415）的导电路径，通过导电接触（451），金属线（459），第二导电接触（453），与晶体管隔离的SOI二极管（411） 409），SOI衬底的体硅层（403）中的P +δ掺杂衬底接触（449）的第三导电接触（455），第二导电线（461）和第四导电接触（457） 。