公开(公告)号：US20040136251A1

公开(公告)日：2004-07-15

申请号：US10751402

申请日：2004-01-06

Applicant: Renesas Technology Corporation ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC: G11C007/00

CPC classification number: G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

Abstract translation: 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US20040117693A1

公开(公告)日：2004-06-17

申请号：US10372970

申请日：2003-02-26

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Naokatsu Moriyama ,  Shigeru Shinohara

IPC: G06F001/04 ,  G06F001/06 ,  G06F001/08 ,  G06F001/12 ,  G06F005/06 ,  G06F011/00

CPC classification number: G06F21/77 ,  G06F21/55 ,  G06F21/755

Abstract: There is provided a technology for preventing disabling of function of a clock monitoring circuit by a hacker in a microcomputer for IC card provided with a clock monitoring circuit as a countermeasure for a hacker. In the microcomputer for IC card provided with the clock monitoring circuit, the clock monitoring circuit is given the function to perform the detecting operation twice during one cycle, namely at the timings of rise and fall of the clock.

Abstract translation: 提供了一种技术，用于防止在设置有时钟监视电路的IC卡的微型计算机中的黑客对时钟监控电路的功能的禁用作为黑客的对策。 在设置有时钟监视电路的IC卡的微计算机中，时钟监视电路具有在一个周期内即时钟上升和下降的定时执行两次检测操作的功能。

公开(公告)号：US20040079996A1

公开(公告)日：2004-04-29

申请号：US10688975

申请日：2003-10-21

Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.

Inventor： Yoichi Tamaki ,  Takayuki Iwasaki ,  Kousuke Tsuji ,  Chiyoshi Kamada

IPC: H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC classification number: H01L27/1203 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/7317

Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.

Abstract translation: 可以通过在SOI衬底1的半导体层中彼此完全电隔离的多个单位双极晶体管Qu的并联连接来减少用于制造半导体器件的设计过程的数量，以形成具有大电流容量的双极晶体管 。

公开(公告)号：US20040066693A1

公开(公告)日：2004-04-08

申请号：US10668229

申请日：2003-09-24

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Junichiro Osako ,  Hirotaka Nishizawa ,  Kenji Osawa ,  Akira Higuchi

IPC: G11C007/00

CPC classification number: H05K3/284 ,  B29C45/14647 ,  B29C45/14655 ,  B29C45/1657 ,  B29C45/1671 ,  B29C2045/1673 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49855 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/01014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/117 ,  H05K2201/10159 ,  H05K2203/1316 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An IC body is loaded to a case 2 made of thermosetting resin material and sealed with a sealing portion made of thermosetting resin material to be integrated, whereby an IC card is manufactured. The IC body comprises: a wiring substrate formed with an external connection terminal at a back surface thereof; a semiconductor chip loaded over a surface of the wiring substrate and electrically connected to the external connection terminal via a interconnect; and the sealing portion made of thermosetting resin material so as to cover the semiconductor chip and a bonding wire. The sealing portion is formed so that the external connection terminal is exposed. The present invention makes it possible to heighten the strength of IC cards and at the same time, to reduce the manufacturing cost and improve the reliability.

Abstract translation: 将IC体装载到由热固性树脂材料制成的壳体2上，并用由热固性树脂材料制成的密封部分密封，从而制造IC卡。 IC体包括：在其背面形成有外部连接端子的布线基板; 半导体芯片，其负载在所述布线基板的表面上，并且经由互连电连接到所述外部连接端子; 以及由热固性树脂材料制成的密封部分以覆盖半导体芯片和接合线。 密封部形成为使外部连接端子露出。 本发明可以提高IC卡的强度，同时降低制造成本，提高可靠性。

公开(公告)号：US20040042269A1

公开(公告)日：2004-03-04

申请号：US10633582

申请日：2003-08-05

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Takayuki Tamura ,  Yoshinori Takase ,  Shinichi Shuto ,  Yasuhiro Nakamura ,  Chiaki Kumahara

IPC: G11C016/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C2211/5641

Abstract: Disclosed is a nonvolatile memory apparatus in which a nonvolatile memory and a controller are mounted and which realizes improved performance of read/write speeds and improved resistance to a retention error. A nonvolatile memory can store information of two bits or more, and can perform a first reading operation of outputting information read from a nonvolatile memory cell as 1-bit information and a second reading operation of outputting the read information as 2-bit information. A controller performs the first reading operation to read first information from the nonvolatile memory and performs the second reading operation to read second information. The reading speed of the first reading operation is faster than that of the second reading operation. In writing to a first area to be read, by using either a voltage in the upper-limit threshold voltage distribution or a voltage in the lower-limit threshold voltage distribution as a threshold voltage, resistance to a retention error of the first information is improved.

Abstract translation: 公开了一种非易失性存储装置，其中安装了非易失性存储器和控制器，并且实现了读/写速度的改进的性能和改进的保持误差的抵抗力。 非易失性存储器可以存储两位以上的信息，并且可以执行将从非易失性存储单元读取的信息作为1位信息输出的第一读取操作和作为2位信息输出读取信息的第二读取操作。 控制器执行第一读取操作以从非易失性存储器读取第一信息，并执行第二读取操作以读取第二信息。 第一读取操作的读取速度比第二读取操作的读取速度更快。 在写入要读取的第一区域中，通过使用上限阈值电压分布中的电压或下限阈值电压分布中的电压作为阈值电压，改善对第一信息的保留误差的抵抗力 。

公开(公告)号：US20040008554A1

公开(公告)日：2004-01-15

申请号：US10616955

申请日：2003-07-11

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Motoki Kanamori ,  Kunihiro Katayama ,  Atsushi Shiraishi ,  Shigeo Kurakata ,  Atsushi Shikata

IPC: G11C007/00

CPC classification number: G11C29/76 ,  G06F11/1068 ,  G11C16/04 ,  G11C16/3431 ,  G11C29/765 ,  G11C29/81 ,  G11C29/82 ,  G11C2029/0411

Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

Abstract translation: 当在包含非易失性存储器和纠错电路的卡存储装置中发生非易失性存储器写入错误时，从非易失性存储器读取写入数据，并且检查错误是否可以通过错误来校正 校正电路。 如果可以纠正错误，则写入操作结束。 如果错误纠正电路无法纠正错误，则执行替代处理以将数据写入其他区域。

公开(公告)号：US20030199122A1

公开(公告)日：2003-10-23

申请号：US10439110

申请日：2003-05-16

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Tsutomu Wada ,  Masachika Masuda

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L21/44 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54406 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, here is disclosed a technique for finding out easily, even after the dicing process, the position of each resin-molded semiconductor device in its former state on the wiring substrate. It includes processing steps of implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.

Abstract translation: 对于其中安装在布线基板上的多个半导体芯片被加工用于块模制的半导体器件的制造，然后将布线基板切割成单独的树脂模制半导体器件，这里公开了一种容易发现的技术，甚至 在切割处理之后，将各树脂模制半导体器件的状态处于布线基板的状态。 其包括对安装在布线基板上的多个半导体芯片实施具有树脂的嵌段成型的处理步骤，之后将布线基板切割成单独的树脂模制半导体器件，其中基板切割步骤之前是附加地址信息图案 到每个树脂模制半导体器件。

公开(公告)号：US20030197277A1

公开(公告)日：2003-10-23

申请号：US10396326

申请日：2003-03-26

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Kenichi Yamamoto ,  Toshiaki Morita ,  Munehiro Yamada ,  Ryosuke Kimoto

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/013 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/244 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: The impact strength resistance of a solder joint portion of a semiconductor device is improved. The semiconductor device has a joint structure wherein a jointing layer which does not contain sulfur substantially is arranged between an underlying conductive layer and a lead-free solder layer and further between the jointing layer and the lead-free solder layer is formed an alloy layer comprising elements of these layers.

Abstract translation: 半导体器件的焊接部的耐冲击强度提高。 半导体器件具有接合结构，其中基本上不含硫的接合层布置在下面的导电层和无铅焊料层之间，并且在接合层和无铅焊料层之间形成合金层，其包括 这些层的元素。

公开(公告)号：US20030153127A1

公开(公告)日：2003-08-14

申请号：US10342238

申请日：2003-01-15

Applicant: Hitachi, Ltd. Hitachi ULSI Systems Co., Ltd.

Inventor： Takashi Wada ,  Kazunari Suzuki ,  Chuichi Miyazaki ,  Toshihiro Shiotsuki ,  Tomoko Higashino

IPC: H01L021/44

CPC classification number: H01L24/83 ,  H01L23/3128 ,  H01L23/3164 ,  H01L23/5387 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/75 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68336 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/13111 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Techniques are provided for preventing occurrence of damage to the top surface of a semiconductor chip at the time of die bonding the semiconductor chip by use of a contact collet. A protection tape is pasted to the top surface of the semiconductor chip before die bonding of the semiconductor chip is executed by pressing the back surface (underside) of the semiconductor chip sucked and securely held by the contact collect against respective chip-mounting regions of a multi-wiring board. The contact collect is, for example, substantially cylindrical in outside shape, and a bottom part (suction head) thereof is made of a soft synthetic rubber, and so forth. The protection tape pasted to pasted to the top surface of the semiconductor chip can prevent the top surface of the semiconductor chip from coming in direct contact with the contact collet even at the time of vacuum suction by pressing the suction head of the contact collect against the top surface of the semiconductor chip.

Abstract translation: 提供技术来防止在使用接触夹头芯片接合半导体芯片时对半导体芯片的顶表面造成的损坏。 将半导体芯片的裸片接合之前，通过将被触点收集并牢固地保持的半导体芯片的背面（下侧）按压到相应的芯片安装区域，将保护带粘贴到半导体芯片的顶表面 多线路板 接触收集体例如是大致圆筒形的外形，其底部（吸头）由软质合成橡胶制成，等等。 粘贴到半导体芯片顶表面上的保护胶带可以防止半导体芯片的顶表面甚至在真空抽吸时直接与接触夹头接触，通过将接触件的吸头压靠 半导体芯片的顶面。

公开(公告)号：US20030142928A1

公开(公告)日：2003-07-31

申请号：US10301641

申请日：2002-11-22

Applicant: Hitachi, Ltd and Hitachi ULSI Systems Co., Ltd.

Inventor： Koji Hirata ,  Masataka Shirai ,  Tomoyoshi Mishima

IPC: G02B006/42

CPC classification number: G02B6/4201 ,  H01L2224/49171 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00

Abstract: The present invention provides a module for optical transmitter formed as an opto-electronic integrated circuit (OEIC) for reducing the heat generated at a driver circuit for modulator and stabilizing the thermal fluctuation in an optical modulator. For promoting the heat dissipation of the top face of the driver circuit for modulator of the OEIC chip, a protruding cooling plate is formed on metal wiring. A part of a semiconductor substrate present between the optical modulator and the driver circuit for modulator is thinned or removed. Further, a carrier for mounting thereon the OEIC chip is divided into two parts, and a peltier cooler is connected to the optical modulator side. This achieves the promotion of heat dissipation from the top face of the driver circuit for modulator, the thermal separation between the optical modulator and the driver circuit for modulator, and the temperature stabilization due to the peltier cooler. The temperature rise and the temperature change of the optical modulator are suppressed, so that it is possible to manufacture a module for optical transmitter showing no characteristic deterioration, in which an optical modulator and a driver circuit for modulator are formed as an OEIC chip.

Abstract translation: 本发明提供了一种用于光发射器的模块，其形成为用于减少用于调制器的驱动电路产生的热量并稳定光调制器中的热波动的光电集成电路（OEIC）。 为了促进OEIC芯片的调制器的驱动电路的顶面的散热，在金属布线上形成突出的冷却板。 存在于调制器的光调制器和驱动电路之间的半导体衬底的一部分被薄化或去除。 此外，用于安装OEIC芯片的载体被分成两部分，并且珀耳替尔冷却器连接到光调制器侧。 这实现了从用于调制器的驱动器电路的顶面，用于调制器的光学调制器和驱动器电路之间的热分离以及由于珀尔帖冷却器引起的温度稳定的散热的促进。 抑制了光调制器的温度上升和温度变化，从而可以制造出没有特征劣化的光发送器模块，其中光调制器和用于调制器的驱动电路形成为OEIC芯片。