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    ELECTROMECHANICAL SYSTEMS PIEZOELECTRIC CONTOUR MODE DIFFERENTIAL AND SINGLE -ENDED RESONATORS AND FILTERS
    21.
    发明申请
    ELECTROMECHANICAL SYSTEMS PIEZOELECTRIC CONTOUR MODE DIFFERENTIAL AND SINGLE -ENDED RESONATORS AND FILTERS 审中-公开
    电动系统压电轮廓模式差分和单向谐振器和滤波器

    公开(公告)号：WO2012030727A1

    公开(公告)日：2012-03-08

    申请号：PCT/US2011/049568

    申请日：2011-08-29

    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  LO, Chi Shun ,  KIM, Jonghae ,  PARK, Sang-June ,  JOO, Sanghoon ,  ZUO, Chengjie ,  YUN, Changhan

    Inventor： LO, Chi Shun ,  KIM, Jonghae ,  PARK, Sang-June ,  JOO, Sanghoon ,  ZUO, Chengjie ,  YUN, Changhan

    IPC: H03H9/00 ,  H03H9/24 ,  H03H9/56

    CPC classification number: H03H9/0095 ,  G09G3/3493 ,  G09G2310/0267 ,  G09G2310/027 ,  H01P1/2135 ,  H03H9/0014 ,  H03H9/02228 ,  H03H9/2431 ,  H03H9/2436 ,  H03H9/2463 ,  H03H9/564 ,  H03H2003/027 ,  H03H2009/02496 ,  H03H2009/02527 ,  H03H2009/241

    Abstract: This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a contour mode resonator device includes a first conductive layer with a plurality of first layer electrodes including a first electrode (2124) at which a first input signal can be provided and a second electrode (2144) at which a first output signal can be provided. A second conductive layer includes a plurality of second layer electrodes including a first electrode (2134) proximate the first electrode of the first conductive layer and a second electrode (2154) proximate the second electrode of the first conductive layer. A second signal can be provided at the first electrode or the second electrode of the second conductive layer to cooperate with the first input signal or the first output signal to define a differential signal. A piezoelectric layer (2108) is disposed between the first conductive layer and the second conductive layer. The piezoelectric layer includes a piezoelectric material. The piezoelectric layer is substantially oriented in a plane and capable of movement in the plane responsive to an electric field between the first electrodes or the second electrodes. The device can be used in the transmission (TX) or receiver (RX) path of a duplexer or as balun.

    Abstract translation: 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 在一个方面，轮廓模式谐振器装置包括具有多个第一层电极的第一导电层，所述第一导电层包括能够提供第一输入信号的第一电极（2124）和第二电极（2144），第二电极 可以提供。 第二导电层包括多个第二层电极，其包括靠近第一导电层的第一电极的第一电极（2134）和靠近第一导电层的第二电极的第二电极（2154）。 可以在第二导电层的第一电极或第二电极处提供第二信号，以与第一输入信号或第一输出信号配合以限定差分信号。 压电层（2108）设置在第一导电层和第二导电层之间。 压电层包括压电材料。 压电层基本上定向在平面中并且能够响应于第一电极或第二电极之间的电场在平面中移动。 该设备可用于双工器的传输（TX）或接收机（RX）路径或平衡 - 不平衡变换器。

    THREE DIMENSIONAL INDUCTOR AND TRANSFORMER DESIGN METHODOLOGY OF GLASS TECHNOLOGY
    23.
    发明申请
    THREE DIMENSIONAL INDUCTOR AND TRANSFORMER DESIGN METHODOLOGY OF GLASS TECHNOLOGY 审中-公开
    玻璃技术的三维电感器和变压器设计方法

    公开(公告)号：WO2011119947A1

    公开(公告)日：2011-09-29

    申请号：PCT/US2011/029978

    申请日：2011-03-25

    Applicant: QUALCOMM Incorporated ,  KIM, Jonghae ,  SHAH, Milind P. ,  LO, Chi Shun ,  LAN, Je-Hsiung ,  LI, Xia ,  NOWAK, Matthew Michael

    Inventor： KIM, Jonghae ,  SHAH, Milind P. ,  LO, Chi Shun ,  LAN, Je-Hsiung ,  LI, Xia ,  NOWAK, Matthew Michael

    IPC: H01L21/02 ,  H01L23/64 ,  H01L27/08 ,  H01L27/12 ,  H01L21/84 ,  H01F17/00 ,  H01F5/00 ,  H01L21/68

    CPC classification number: H01L28/10 ,  H01F2017/004 ,  H01L21/84 ,  H01L23/645 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed is an inductor or transformer for use in integrated circuit devices that includes a high - resistivity substrate. The inductor (1100) includes a plurality of conductive traces (1110, 1112, 1114) around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid- shaped. Some of the conductive traces can be formed during back- end- of - line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid- shaped. The first conductive path can be interleaved with the second conductive path.

    Abstract translation: 公开了一种用于集成电路器件的电感器或变压器，其包括高电阻率衬底。 电感器（1100）包括围绕衬底的多个导电迹线（1110,1112,1114），其形成从第一端口到第二端口的连续导电路径。 导电路径可以是螺线管形的。 一些导电迹线可以在集成电路管芯的后端处理或背面电镀中形成。 变压器包括具有输入和输出端口的第一电感器和它们之间的第一连续导电路径; 以及具有输入和输出端口的第二电感器以及它们之间的第二连续导电路径。 第二电感器与第一电感器无关并与其电磁耦合。 第一和第二导电路径可以是螺线管形的。 第一导电路径可以与第二导电路径交错。

    HETEROGENEOUS TECHNOLOGY INTEGRATION
    24.
    发明申请
    HETEROGENEOUS TECHNOLOGY INTEGRATION 审中-公开
    异构技术整合

    公开(公告)号：WO2011119932A1

    公开(公告)日：2011-09-29

    申请号：PCT/US2011/029955

    申请日：2011-03-25

    Applicant: QUALCOMM Incorporated ,  KIM, Jonghae ,  GOUSEV, Evgeni P. ,  NOWAK, Matthew Michael

    Inventor： KIM, Jonghae ,  GOUSEV, Evgeni P. ,  NOWAK, Matthew Michael

    IPC: H01L25/065

    CPC classification number: H01L25/0655 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L29/0657 ,  H01L2224/16105 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/92227 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump.

    Abstract translation: 具有由多种技术制成的至少一层的异质集成电路以及制造异质集成电路的方法。 异质集成电路包括封装衬底，第一技术的第一裸片和第二技术的第二裸片，其中两个裸片位于同一层。 一个模具可以围绕另一个模具。 异质集成电路还可以包括耦合两个管芯的引线接合和/或水平微凸块。 异质集成电路还可以包括引线接合或将一个管芯耦合到封装衬底的垂直微突起。 垂直微凸块耦合可以包括通孔。 这两种技术可以是包括CMOS，玻璃，蓝宝石和石英在内的各种技术。 一个管芯也可以在同一层上与另一个管芯相邻，并且两个管芯使用水平微型焊盘进行耦合。

    HIGH BREAKDOWN VOLTAGE EMBEDDED MIM CAPACITOR STRUCTURE
    25.
    发明申请
    HIGH BREAKDOWN VOLTAGE EMBEDDED MIM CAPACITOR STRUCTURE 审中-公开
    高突破电压嵌入式MIM电容结构

    公开(公告)号：WO2011017623A1

    公开(公告)日：2011-02-10

    申请号：PCT/US2010/044724

    申请日：2010-08-06

    Applicant: QUALCOMM Incorporated ,  KANG, Wootag ,  KIM, Jonghae

    Inventor： KANG, Wootag ,  KIM, Jonghae

    IPC: H01L21/02 ,  H01L27/08 ,  H01L27/10

    CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L27/101

    Abstract: Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device includes gate material (204) embedded in an insulator, (209) a plurality of metal contacts, (213) and a plurality of capacitors. (C1-C4) The plurality of capacitors includes a lower electrode, (217) a dielectric (219) formed so as to cover a surface of the lower electrode, and an upper electrode (221b, c) formed on the dielectric. Further, the plurality of contacts connects each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors are connected in series via the gate material.

    Abstract translation: 提出了与多个高击穿电压嵌入式电容器相关的方法和装置。 半导体器件包括嵌入绝缘体中的栅极材料（204），（209）多个金属触点（213）和多个电容器。 （C1-C4）多个电容器包括下电极，（217）形成为覆盖下电极的表面的电介质（219）和形成在电介质上的上电极（221b，c）。 此外，多个触点将多个电容器中的每个下电极连接到栅极材料。 多个电容器通过栅极材料串联连接。

    MONITORING RELIABILITY OF A DIGITAL SYSTEM
    26.
    发明申请
    MONITORING RELIABILITY OF A DIGITAL SYSTEM 审中-公开
    监测数字系统的可靠性

    公开(公告)号：WO2008122459A3

    公开(公告)日：2008-11-27

    申请号：PCT/EP2008052021

    申请日：2008-02-19

    Applicant: IBM ,  IBM UK ,  KIM DAE IK ,  KIM JONGHAE ,  KIM MOON JU ,  MOULIC JAMES RANDAL ,  SONG HONG HUA

    Inventor： KIM DAE IK ,  KIM JONGHAE ,  KIM MOON JU ,  MOULIC JAMES RANDAL ,  SONG HONG HUA

    IPC: G06F11/00

    CPC classification number: G06F11/008

    Abstract: Method, system and computer program are provided for continually monitoring reliability of a digital system and for issuing a warning signal if digital system operation degrades to or past a specified threshold. The technique includes periodically determining a maximum frequency of operation of the digital system, and generating a warning signal indicative of a reliability degradation of the digital system if at least one of: (i) a measured or estimated maximum frequency of operation of the digital system is below a warning threshold frequency of operation of the digital system, wherein the warning threshold frequency is greater than or equal to a manufacturer specified minimum frequency of operation for the digital system; or (ii) a rate of change in the difference between measured maximum frequencies of operation of the digital system exceeds an acceptable rate of change threshold for the digital system.

    Abstract translation: 提供了方法，系统和计算机程序，用于连续监视数字系统的可靠性，并且如果数字系统操作降级到或超过指定阈值，则发出警告信号。 该技术包括周期性地确定数字系统的最大操作频率，以及产生指示数字系统的可靠性劣化的警告信号，如果以下至少一个：（i）数字系统的测量或估计的最大操作频率 低于数字系统的警告阈值操作频率，其中警告阈值频率大于或等于制造商规定的数字系统的最小操作频率; 或者（ii）数字系统的测量的最大操作频率之间的差异的变化率超过数字系统的可接受的变化率阈值。

    DESIGN RULES FOR ON-CHIP INDUCTORS
    27.
    发明申请
    DESIGN RULES FOR ON-CHIP INDUCTORS 审中-公开
    片上电感设计规范

    公开(公告)号：WO2008037634B1

    公开(公告)日：2008-05-15

    申请号：PCT/EP2007059858

    申请日：2007-09-18

    Applicant: IBM ,  IBM UK ,  CHO CHOONGYEUN ,  KIM DAEIK ,  KIM JONGHAE ,  KIM MOON JU ,  PLOUCHART JEAN-OLIVIER ,  TRZCINSKI ROBERT

    Inventor： CHO CHOONGYEUN ,  KIM DAEIK ,  KIM JONGHAE ,  KIM MOON JU ,  PLOUCHART JEAN-OLIVIER ,  TRZCINSKI ROBERT

    IPC: H01L21/02 ,  G06F17/50 ,  H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L23/64 ,  H01L27/02

    CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more of chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

    Abstract translation: 提供用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化芯片产量，芯片性能，芯片制造性和电感器Q因子参数中的一个或多个。

    METHOD AND SYSTEMS FOR COPYING DATA COMPONENTS BETWEEN NODES OF A NETWORK
    29.
    发明申请
    METHOD AND SYSTEMS FOR COPYING DATA COMPONENTS BETWEEN NODES OF A NETWORK 审中-公开
    用于复制网络节点之间的数据组件的方法和系统

    公开(公告)号：WO2006032678A1

    公开(公告)日：2006-03-30

    申请号：PCT/EP2005/054727

    申请日：2005-09-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  CHOY, Eric, Yee, Teck ,  KIM, Moon ,  KIM, Jonghae

    Inventor： CHOY, Eric, Yee, Teck ,  KIM, Moon ,  KIM, Jonghae

    IPC: H04L12/24 ,  H04L12/56

    CPC classification number: H04W28/14 ,  H04L41/06 ,  H04L41/12 ,  H04L45/02 ,  H04L67/12 ,  H04L67/125 ,  H04L69/40 ,  H04W4/70 ,  H04W92/18

    Abstract: Under the present invention, a wireless sensor network comprising a plurality of peer to peer nodes is provided. Each node in the network includes, among other things, a sensor for detecting environmental factors. When a potential failure is detected within a node, the node will query its neighboring nodes to determine whether they have the capability to store any data component(s) currently stored within the potentially failing node. Based on the querying, the data component(s) in the potentially failing node are copied to one or more of the neighboring nodes. Thereafter, details of the copying can be broadcast to other nodes in the network, and any routing tables that identify the locations of data components stored throughout the wireless sensor network can be updated.

    Abstract translation: 在本发明中，提供了包括多个对等节点的无线传感器网络。 网络中的每个节点尤其包括用于检测环境因素的传感器。 当在节点内检测到潜在的故障时，节点将查询其相邻节点以确定它们是否具有存储当前存储在潜在故障节点内的任何数据组件的能力。 基于查询，可能故障节点中的数据组件被复制到一个或多个相邻节点。 此后，复制的细节可以广播到网络中的其他节点，并且可以更新识别存储在整个无线传感器网络中的数据组件的位置的任何路由表。

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