公开(公告)号：WO2007149581A8

公开(公告)日：2007-12-27

申请号：PCT/US2007/014684

申请日：2007-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  KIEWRA, Edward, W. ,  KOESTER, Steven, J. ,  SADANA, Devendra, K. ,  SHAHIDI, Ghavam ,  SUN, Yanning

Inventor： KIEWRA, Edward, W. ,  KOESTER, Steven, J. ,  SADANA, Devendra, K. ,  SHAHIDI, Ghavam ,  SUN, Yanning

IPC: H01L21/338

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the πi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

公开(公告)号：WO2006116098A2

公开(公告)日：2006-11-02

申请号：PCT/US2006/015107

申请日：2006-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DESOUZA, Joel P. ,  SADANA, Devendra K. ,  SAENGER, Katherine L. ,  SUNG, Chun-yung ,  YANG, Min ,  YIN, Haizhou

Inventor： DESOUZA, Joel P. ,  SADANA, Devendra K. ,  SAENGER, Katherine L. ,  SUNG, Chun-yung ,  YANG, Min ,  YIN, Haizhou

IPC: H01L27/12

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

Abstract translation: 混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET） 以半导体方向设置，其对于空穴迁移率是最佳的。 本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。 描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。 可以并入其中可并入这些新的FET的混合基板及其制造方法。

公开(公告)号：WO2006017640B1

公开(公告)日：2006-04-27

申请号：PCT/US2005027691

申请日：2005-08-04

Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer (41) of Si or Ge is deposited on a substrate (10) in a first depositing step; a second layer (42) of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer (50) having a plurality of Si layers and a plurality of Ge layers (41-44). The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer. The combined SiGe layer (50) is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer (61) on the combined SiGe layer (50); the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer (61) is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.

Abstract translation: 公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。 在第一沉积步骤中，在衬底（10）上沉积Si或Ge的第一层（41） 在第二沉积步骤中将另一元素的第二层（42）沉积在第一层上; 并重复第一沉积步骤和第二沉积步骤以形成具有多个Si层和多个Ge层（41-44）的组合SiGe层（50）。 Si层和Ge层的各自厚度符合组合SiGe层的所需组成比。 组合的SiGe层（50）的特征在于Si和Ge的数字合金，其导热率大于Si和Ge的无规合金的导热率。 该方法可以进一步包括在组合的SiGe层（50）上沉积Si层（61）的步骤; 组合的SiGe层的特征在于弛豫SiGe层，并且Si层（61）是应变Si层。 为了在SiGe层中具有更大的导热性，可以沉积第一层和第二层，使得每个层基本上由单一的同位素组成。

公开(公告)号：WO2005078786A1

公开(公告)日：2005-08-25

申请号：PCT/US2004/001555

申请日：2004-01-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHEN, Huajie ,  BEDELL, Stephen, W. ,  SADANA, Devendra, K. ,  MOCUTA, Dan, M.

Inventor： CHEN, Huajie ,  BEDELL, Stephen, W. ,  SADANA, Devendra, K. ,  MOCUTA, Dan, M.

IPC: H01L21/331

CPC classification number: H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/31658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78687

Abstract: A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer (104) is deposited (300) on an SOI wafer (102, 100). Thermal mixing of the SiGe and Si layers is performed (302) to form a thick SGOI (106) with high relaxation and low stacking fault defect density. The SiGe layer (110) is then thinned (306) to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si (112) is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550°C-700°C) HIPOX or steam oxidation, in-situ HCI etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCI, DCS and GeH4.

Abstract translation: 一种形成绝缘体上硅锗（SGOI）结构的方法。 在SOI晶片（102,100）上沉积SiGe层（104）（300）。 执行SiGe和Si层的热混合（302）以形成具有高松弛和低堆垛层错缺陷密度的厚SGOI（106）。 然后将SiGe层（110）变薄（306）至期望的最终厚度。 稀释过程，Ge浓度，松弛量和堆垛层错缺陷密度均不变。 因此获得了具有高松弛和低堆垛层错缺陷密度的薄SGOI膜。 然后将Si（112）层沉积在薄SGOI晶片上。 稀释方法包括低温​​（550℃-700℃）HIPOX或蒸汽氧化，在外延室或CMP中的原位HCl蚀刻。 由HIPOX或蒸汽氧化稀化产生的粗糙SiGe表面在应变Si沉积期间用接触式CMP，原位氢气烘烤和SiGe缓冲层进行平滑化，或在氢气环境中用HCl混合气体DCS 和GeH4。

公开(公告)号：WO2004109776A2

公开(公告)日：2004-12-16

申请号：PCT/US2004/016903

申请日：2004-05-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BEDELL, Stephen, W. ,  CHEN, Huajie ,  FOGEL, Keith, E. ,  SADANA, Devendra, K.

Inventor： BEDELL, Stephen, W. ,  CHEN, Huajie ,  FOGEL, Keith, E. ,  SADANA, Devendra, K.

IPC: H01L21/00

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  Y10T428/12674

Abstract: The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.

Abstract translation: 本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。 该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值， 一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。 根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。

公开(公告)号：WO2003063229A1

公开(公告)日：2003-07-31

申请号：PCT/US2003/001431

申请日：2003-01-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BEDELL, Stephen, W. ,  CHU, Jack, O. ,  FOGEL, Keith, E. ,  KOESTER, Stephen, J. ,  SADANA, Devendra, K. ,  OTT, John, Albrecht

Inventor： BEDELL, Stephen, W. ,  CHU, Jack, O. ,  FOGEL, Keith, E. ,  KOESTER, Stephen, J. ,  SADANA, Devendra, K. ,  OTT, John, Albrecht

IPC: H01L21/331

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/2251 ,  H01L21/324 ,  H01L27/1203 ,  H01L29/66916 ,  Y10S438/938 ,  Y10T428/12674 ,  Y10T428/265 ,  Y10T428/31848

Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate (10) material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to the diffusion of Ge. Optionally forming a Si cap layer (18) over the SiGe or pure Ge layer (16), and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughtout the first single crystal Si layer (14), the optional Si cap (18) and the SiGe or pure Ge layer (16) thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer (12). Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate material are also disclosed herein.

Abstract translation: 提供一种形成薄的，高质量的松散的绝缘体上硅衬底（10）材料的方法，其首先包括在第一单晶Si层（14）的表面上形成SiGe或纯Ge层 阻挡层（12），其抵抗Ge的扩散。 可选地，在SiGe或纯Ge层（16）上形成Si覆盖层（18），然后在允许Ge透过第一单晶硅层（14），可选Si帽（ 18）和SiGe或纯Ge层（16），从而在阻挡层（12）的顶部形成基本松弛的单晶SiGe层。 附加的SiGe再生长和/或应变外延层的形成可以遵循上述步骤。 绝缘体上硅衬底材料以及至少包括绝缘体上硅衬底材料的结构也在本文中公开。

公开(公告)号：WO2012173814A1

公开(公告)日：2012-12-20

申请号：PCT/US2012/040873

申请日：2012-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ABOU-KANDIL, Ahmed ,  FOGEL, Keith, E. ,  HONG, Augustin, J. ,  KIM, Jeehwan ,  SADANA, Devendra, K.

Inventor： ABOU-KANDIL, Ahmed ,  FOGEL, Keith, E. ,  HONG, Augustin, J. ,  KIM, Jeehwan ,  SADANA, Devendra, K.

IPC: H01L31/00

CPC classification number: H01L31/077 ,  H01L31/075 ,  H01L31/1812 ,  H01L31/1824 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

Abstract: A photovoltaic device and method for fabricating a photovoltaic device include forming a light-absorbing semiconductor structure on a transmissive substrate including a first doped layer (406) and forming an intrinsic layer (410) on the first doped layer, wherein the intrinsic layer includes an amorphous material. The intrinsic layer is treated (412) with a plasma to form seed sites. A first tunnel junction layer is formed (414) on the intrinsic layer by growing microcrystals from the seed sites.

Abstract translation: 一种用于制造光伏器件的光电器件和方法包括在包括第一掺杂层（406）的透射衬底上形成光吸收半导体结构，并在第一掺杂层上形成本征层（410），其中本征层包括 无定形材料。 用等离子体处理（412）本征层以形成种子位点。 通过从种子位点生长微晶，在本征层上形成第一隧道结层（414）（414）。

公开(公告)号：WO2010016956A1

公开(公告)日：2010-02-11

申请号：PCT/US2009/041506

申请日：2009-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DE SOUZA, Joel, P. ,  HOVEL, Harold, John ,  INNS, Daniel, A. ,  SADANA, Devendra, K. ,  SHAHIDI, Ghavam, G.

Inventor： DE SOUZA, Joel, P. ,  HOVEL, Harold, John ,  INNS, Daniel, A. ,  SADANA, Devendra, K. ,  SHAHIDI, Ghavam, G.

IPC: H01L21/322

CPC classification number: H01L21/3225 ,  H01L21/02032

Abstract: A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200°C or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.

Abstract translation: 描述了一种用于改善其中具有金属污染物的含硅晶片的少数寿命的方法，其包括在1200℃或更高温度下退火并提供氧气，惰性气体和含氯气体如HCl的气态环境。

公开(公告)号：WO2006116098A3

公开(公告)日：2008-10-30

申请号：PCT/US2006015107

申请日：2006-04-21

Applicant: IBM ,  DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: In the claimed mixed-crystal-orientation channel FET, source/drain regions above the bonded interface 360 have the orientation of the upper semiconductor 350 and source/drain regions below the bonded interface 360 have the orientation of the lower semiconductor 370, so that each part of the source/drain has the same crystal orientation as the semiconductor material laterally adjacent to it. Optional source/drain extensions 392 are disposed entirely in the upper semiconductor layer 350. Optionally, the bonded interface 360 is situated towards the bottom of source/drain regions 380, leaving source/drains 380 mostly in upper semiconductor layer 350.

Abstract translation: 在所要求的混晶取向沟道FET中，键合界面360上方的源极/漏极区域具有上部半导体350的取向，并且键合界面360下方的源极/漏极区域具有下部半导体370的取向，使得每个 源极/漏极的一部分具有与横向相邻的半导体材料相同的晶体取向。 可选的源极/漏极延伸部分392完全设置在上部半导体层350中。可选地，接合界面360朝向源极/漏极区域380的底部设置，使得源极/漏极380大部分在上部半导体层350中。

公开(公告)号：WO2005034209A3

公开(公告)日：2005-05-19

申请号：PCT/US2004031823

申请日：2004-09-28

Applicant: IBM ,  CHOE KWANG SU ,  FOGEL KEITH E ,  MAURER SIEGFRIED L ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

Inventor： CHOE KWANG SU ,  FOGEL KEITH E ,  MAURER SIEGFRIED L ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/265 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/762 ,  H01L21/20

CPC classification number: H01L21/76243 ,  H01L21/26533 ,  H01L21/3063 ,  H01L21/31662

Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

Abstract translation: 提供了一种制造在含Si的上层下方具有薄但均匀的掩埋氧化物区域的硅绝缘体（SOI）的方法。 通过首先修饰含Si衬底的表面以包含大量的空位或空隙的浓度来制造SOI结构。 接下来，含硅层通常但不总是形成在衬底顶上，然后使用低氧剂量将氧离子注入到结构中。 然后将结构退火以将注入的氧离子转化成薄但均匀的热掩埋氧化物区域。