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    FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS
    22.
    发明申请
    FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS 审中-公开
    在具有不同晶体取向的颗粒的含CU连接元件上形成可靠的扩散阻挡层

    公开(公告)号：WO2008107419A1

    公开(公告)日：2008-09-12

    申请号：PCT/EP2008/052565

    申请日：2008-03-03

    Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  TORRES, Joaquin ,  GOSSET, Laurent ,  CHHUN, Sonarith ,  ARNAL, Vincent

    Inventor： TORRES, Joaquin ,  GOSSET, Laurent ,  CHHUN, Sonarith ,  ARNAL, Vincent

    IPC: H01L21/768 ,  H01L21/321

    CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76889

    Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystalorientations, comprisesselectively incorporating Si into only a first set of crystallites withat least one first crystalorientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier- cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.

    Abstract translation: 本发明涉及一种在含Cu互连元件上制造扩散阻挡帽的方法，该方法具有至少两种不同晶体取向的晶体，其包括仅将第一组晶体中的Si并入至少一种第一晶体取向中， 条件，并且随后选择性地形成包含CuSi和第一扩散阻挡层部分的第一粘附层部分，仅在第一组微晶上形成第一屏蔽帽部分，随后选择性地将Si并入仅第二组 的微晶，使用与第一工艺条件不同的第二工艺条件，以及在互连元件的第二组微晶上形成包含含Si的第二扩散阻挡层部分的第二阻挡帽部分。 该处理改善了扩散阻挡帽的性质，并确保了互连元件上的扩散阻挡层的连续形成。

    TEST STRUCTURE FOR DETECTION OF DEFECT DEVICES WITH LOWERED RESISTANCE
    24.
    发明申请
    TEST STRUCTURE FOR DETECTION OF DEFECT DEVICES WITH LOWERED RESISTANCE 审中-公开
    用于检测具有较低电阻的缺陷设备的测试结构

    公开(公告)号：WO2008052940A2

    公开(公告)日：2008-05-08

    申请号：PCT/EP2007/061537

    申请日：2007-10-26

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  DE VRIES, Dirk Kenneth ,  GONELLA, Roberto Maurizio

    Inventor： DE VRIES, Dirk Kenneth ,  GONELLA, Roberto Maurizio

    CPC classification number: G01R31/2884 ,  G01R31/2831 ,  H01L22/34 ,  H01L2924/3011

    Abstract: The present invention relates to a test structure that comprises at least two devices under test DUT, which respectively have a first electrical device resistance in a non- defect state and a second electrical device resistance in defect state, the first being higher than the second electrical device resistance. In the test structure the DUTs are connected in parallel to a first test contact pad via a first conducting line and connected in parallel to a second test contact pad via a second conducting line, and respectively connected to the first conducting line via respective first test resistors, which have known respective electrical test resistances, such that a total electrical resistance between the first an second test contact pads is indicative of the number of DUTs, which have the second electrical device resistance. The test structure allows testing a larger number of DUTs in parallel in a single measurement.

    Abstract translation: 本发明涉及一种测试结构，该测试结构包括至少两个被测试器件，它们分别具有处于非缺陷状态的第一电子器件电阻和处于缺陷状态的第二电子器件电阻，第一器件电阻高于第二电气 器件电阻。 在测试结构中，DUT通过第一导电线并联连接到第一测试接触焊盘，并经由第二导线并联连接到第二测试接触焊盘，并且经由相应的第一测试电阻器分别连接到第一导线 其已知各自的电测试电阻，使得第一和第二测试接触焊盘之间的总电阻指示具有第二电气设备电阻的DUT的数量。 测试结构允许在单次测量中并行测试更多的DUT。

    METHOD FOR TRANSFERRING A PREDETERMINED PATTERN REDUCING PROXIMITY EFFECTS
    25.
    发明申请
    METHOD FOR TRANSFERRING A PREDETERMINED PATTERN REDUCING PROXIMITY EFFECTS 审中-公开
    用于传输预测图案减少接近效应的方法

    公开(公告)号：WO2007129135A1

    公开(公告)日：2007-11-15

    申请号：PCT/IB2006/001670

    申请日：2006-05-05

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ,  ST MICROELECTRONICS (Crolles 2) SAS ,  FREESCALE SEMICONDUCTOR, INC. ,  PAIN, Laurent ,  MANAKLI, Serdar ,  BERVIN, Georges

    Inventor： PAIN, Laurent ,  MANAKLI, Serdar ,  BERVIN, Georges

    IPC: G03F7/20

    CPC classification number: G03F7/70433 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/70383 ,  H01J37/3174 ,  Y10S430/143

    Abstract: A method for transferring a predetermined pattern onto a flat support performed by direct writing by means of a particle beam comprises at least: deposition of a photoresist layer on a free surface of the support, application of the beam on exposed areas of the photoresist layer, performing correction by modulation of exposure doses received by each exposed area, developing of the photoresist layer so as to form said pattern. Correction further comprises determination of a substitution pattern (11) comprising at least one subresolution feature and use of the substitution pattern (11) for determining the areas to be exposed when the electron beam is applied. In addition, modulation takes account of the density of the substitution pattern (11) near to each exposed area.

    Abstract translation: 通过用粒子束进行直接写入而将预定图案转移到平坦支撑件上的方法至少包括：在支撑体的自由表面上沉积光致抗蚀剂层，在光致抗蚀剂层的曝光区域上施加光束， 通过调制由每个曝光区域接收的曝光剂量来校正光致抗蚀剂层的显影以形成所述图案。 校正还包括确定包含至少一个子分解特征的取代图案（11），并且使用取代图案（11）来确定当施加电子束时要暴露的区域。 此外，调制考虑了靠近每个暴露区域的取代图案（11）的密度。

    CO-INTEGRATION OF MULTI-GATE FET WITH OTHER FET DEVICES IN CMOS TECHNOLOGY
    26.
    发明申请
    CO-INTEGRATION OF MULTI-GATE FET WITH OTHER FET DEVICES IN CMOS TECHNOLOGY 审中-公开
    CMOS技术中多栅极FET与其他FET器件的集成

    公开(公告)号：WO2007115954A1

    公开(公告)日：2007-10-18

    申请号：PCT/EP2007/053106

    申请日：2007-03-30

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS CROLLES 2 SAS ,  POUYDEBASQUE, Arnaud ,  CERUTTI, Robin

    Inventor： POUYDEBASQUE, Arnaud ,  CERUTTI, Robin

    IPC: H01L27/12 ,  H01L21/84 ,  H01L29/04 ,  H01L29/786

    CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/785

    Abstract: The present invention relates to a CMOS circuit device on a SOI substrate with an oriented silicon surface, comprising on a first substrate region a FET that has a FET channel region of a first conductivity type, and comprising on a second substrate region a FinFET that has a FinFET channel region of a second conductivity type which is opposite to the first conductivity type. The invention also relates to a method for fabricating such a CMOS circuit device. The fabrication of the multi-gate planar FET comprises, at an intermediate step, forming a FET channel stack with an alternating sequence of layers of a FET material and of a sacrificial material and containing main FET -channel faces, which have the same orientation as the oriented silicon surface. According to the invention, a co-integration of multi-gate FET devices is achieved that ensures high carrier mobilities for both NMOS and PMOS FETs.

    Abstract translation: 本发明涉及具有取向硅表面的SOI衬底上的CMOS电路器件，在第一衬底区域上包括具有第一导电类型的FET沟道区的FET，并且在第二衬底区域上包括具有 与第一导电类型相反的第二导电类型的FinFET沟道区。 本发明还涉及制造这种CMOS电路器件的方法。 多栅平面FET的制造包括在中间步骤中，形成具有FET材料和牺牲材料的层的交替序列并且包含主FET沟道面的FET沟道堆叠，其具有与 定向硅表面。 根据本发明，实现了多栅极FET器件的共同集成，确保了NMOS和PMOS FET两者的高载流子迁移率。

    PHASE MODULATOR DEVICE AND METHOD
    28.
    发明公开
    PHASE MODULATOR DEVICE AND METHOD 审中-公开

    公开(公告)号：US20230236446A1

    公开(公告)日：2023-07-27

    申请号：US18295121

    申请日：2023-04-03

    Applicant: ST Microelectronics (Crolles 2) SAS

    Inventor： Sébastien Cremer ,  Frédéric Boeuf ,  Stephane Monfray

    IPC: G02F1/035 ,  G02B6/12 ,  G02F1/01

    CPC classification number: G02F1/035 ,  G02B6/12004 ,  G02F1/0147 ,  G02F2201/063

    Abstract: The present disclosure relates to a method including the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.

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