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    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
    27.
    发明申请
    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS 审中-公开
    通过基板VIAS集成的金属接线结构

    公开(公告)号：WO2010017062A1

    公开(公告)日：2010-02-11

    申请号：PCT/US2009/051908

    申请日：2009-07-28

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COLLINS, David, S. ,  JOSEPH, Alvin ,  LINDGREN, Peter, J. ,  STAMPER, Anthony, K. ,  WATSON, Kimball, M.

    Inventor： COLLINS, David, S. ,  JOSEPH, Alvin ,  LINDGREN, Peter, J. ,  STAMPER, Anthony, K. ,  WATSON, Kimball, M.

    IPC: H01L23/522

    CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: An array of through substrate vias (TSVs) (20) is formed through a semiconductor substrate (12) and a contact- via-level dielectric layer (50) thereupon. A metal-wire-level dielectric layer (60) and a line-level metal wiring structure (80) embedded therein are formed directly on the contact-via-level dielectric layer (50). The line-level metal wiring structure (80) includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer (60). In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs (20) to maximize the contact area between the TSVs (20) and the line-level metal wiring structure (80). In another embodiment, a set of cheesing holes overlying an entirety of seams (18) in the array of TSVs (20) is formed to prevent trapping of any plating solution in the seams (19)of the TSVs (20) during plating to prevent corrosion of the TSVs (20)at the seams (19).

    Abstract translation: 穿过衬底通孔（TSV）（20）的阵列通过半导体衬底（12）和接触通过级介电层（50）在其上形成。 直接在接触通路层电介质层（50）上形成金属线层介电层（60）和嵌入其中的线状金属布线结构（80）。 线状金属布线结构（80）包括填充有金属线层介电层（60）的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV（20）阵列的区域的外侧，以最大化TSV（20）和线路级金属布线结构（80）之间的接触面积。 在另一个实施例中，形成了覆盖在TSV（20）阵列中的整个接缝（18）的一组烘干孔，以防止在电镀期间捕获TSV（20）的接缝（19）中的任何电镀溶液以防止 接缝处的TSV（20）的腐蚀（19）。

    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER
    28.
    发明申请
    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER 审中-公开
    通过包括插入式灌装机在内的基板

    公开(公告)号：WO2009102741A1

    公开(公告)日：2009-08-20

    申请号：PCT/US2009/033723

    申请日：2009-02-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LINDGREN, Peter, J. ,  SPROGIS, Edmund, J. ,  STAMPER, Anthony, K. ,  STEIN, Kenneth, J.

    Inventor： LINDGREN, Peter, J. ,  SPROGIS, Edmund, J. ,  STAMPER, Anthony, K. ,  STEIN, Kenneth, J.

    IPC: H01L23/48

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through substrate (10) via includes an annular conductor layer at a periphery of a through substrate (10) aperture, and a plug layer (24) surrounded by the annular conductor layer. A method for fabricating the through substrate (10) via includes forming a blind aperture within a substrate (10) and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer (20) that does not fill the aperture and plug layer (24) that does fill the aperture. The backside of the substrate (10) may then be planarized to expose at least the planarized conformal conductor layer. (20)

    Abstract translation: 贯穿基板（10）通孔包括在通孔基板（10）的周边的环形导体层和由环形导体层包围的插塞层（24）。 一种用于制造穿透基底（10）通孔的方法，包括在基底（10）内形成盲孔，并且在盲孔内依次形成并随后在盲孔内平坦化形成不填充孔径和塞子层（24）的共形导体层（20） ），其中填充了孔径。 然后可以将衬底（10）的背面平坦化以至少露出平坦化的共形导体层。 （20）

    STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETS
    29.
    发明申请
    STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETS 审中-公开
    紧凑型长通道FET的结构和方法

    公开(公告)号：WO2009061698A1

    公开(公告)日：2009-05-14

    申请号：PCT/US2008/082226

    申请日：2008-11-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DORIS, Bruce, B. ,  RADENS, Carl, J. ,  STAMPER, Anthony, K.

    Inventor： DORIS, Bruce, B. ,  RADENS, Carl, J. ,  STAMPER, Anthony, K.

    IPC: H01L29/00

    CPC classification number: H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

    Abstract: A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate (12) in which the at least one FET includes a long channel length and/or a wide channel width (11) and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.

    Abstract translation: 一种紧凑的半导体结构，包括位于半导体衬底（12）的表面之上和之内的至少一个FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度（11），以及制造 同样提供。 在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。 在这样的实施例中，FET具有长的沟道长度。 在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。 在这样的实施例中，FET具有宽的通道宽度。 在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。 在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION
    30.
    发明申请
    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
    在半导体制造中去除蚀刻工艺残留

    公开(公告)号：WO2008091923A2

    公开(公告)日：2008-07-31

    申请号：PCT/US2008/051758

    申请日：2008-01-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HERRIN, Russell, T. ,  LINDGREN, Peter, J. ,  STAMPER, Anthony, K.

    Inventor： HERRIN, Russell, T. ,  LINDGREN, Peter, J. ,  STAMPER, Anthony, K.

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/5223 ,  H01L21/02063 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

    Abstract translation: 半导体结构及其形成方法。 半导体制造方法包括提供结构的步骤。 一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域， 介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。 该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。 然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

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