公开(公告)号：EP1804159A1

公开(公告)日：2007-07-04

申请号：EP05078050.1

申请日：2005-12-30

Applicant: STMicroelectronics Belgium N.V.

Inventor： Himpe, Vincent

IPC: G06F5/06

CPC classification number: G06F5/06

Abstract: A serial in random out memory circuit has a number of memory cells (10) integrated with write control circuitry (decoder1, decoder 2, 20) for writing a sequence of data inputs to sequential locations in the memory cells. Read control circuitry (decoder1, decoder 2, 20) is integrated to receive address signals from an external device and provide a random access read output from the memory cells, mapped into an address range of the external device. Compared to circuits using discrete components and conventional RAM chips, the integrated SIRO can enable some of the circuitry or external software to be dispensed with and so reduce costs or increase performance. The memory cells can be arranged in a number of blocks, selectable one at a time for mapping to the external device address range.

Abstract translation: 串行随机输出存储器电路具有与写入控制电路（解码器1，解码器2,20）集成的多个存储器单元（10），用于将数据输入序列写入存储器单元中的顺序位置。 读取控制电路（解码器1，解码器2,20）被集成以从外部设备接收地址信号，并且提供映射到外部设备的地址范围的来自存储器单元的随机存取读取输出。 与使用分立元件和常规RAM芯片的电路相比，集成SIRO可以使部分电路或外部软件得以免除，从而降低成本或提高性能。 存储器单元可以被布置在多个块中，一次可选地用于映射到外部设备地址范围。

公开(公告)号：EP1708091A1

公开(公告)日：2006-10-04

申请号：EP05447073.7

申请日：2005-03-31

Applicant: STMicroelectronics Belgium N.V.

Inventor： Alexandre, Rudolph

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/161 ,  G06F13/1684

Abstract: A memory system for use with a master-slave type bus such as an AHB bus (30) has a memory (60), a bus interface (130) to allow memory access from the bus, and a direct memory access interface (130) to allow memory access from a DMA controller without occupying the bus. Compared to the known DMA arrangement, it can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter (130) can arbitrate between the memory accesses and give priority to DMA accesses.

Abstract translation: 一种与诸如AHB总线（30）的主从型总线一起使用的存储器系统具有存储器（60），允许来自总线的存储器访问的总线接口（130）和直接存储器访问接口（130） 以允许来自DMA控制器的存储器访问而不占用总线。 与已知的DMA布置相比，它可以减少总线的占用，它可以允许专用DMA访问协议比使用总线协议更快，并且可以消除或减少对总线仲裁及相关电路和延迟的需要。 仲裁器（130）可以在存储器访问之间仲裁并给予DMA访问优先级。

公开(公告)号：EP1422827B1

公开(公告)日：2006-01-18

申请号：EP02447228.4

申请日：2002-11-21

Applicant: STMicroelectronics Belgium N.V.

Inventor： Craninckx, Jan Frans Lucien

IPC: H03L7/18 ,  H03L7/099 ,  H03L7/081 ,  H03L7/089

CPC classification number: H03L7/18 ,  H03L7/081 ,  H03L7/0893 ,  H03L7/0996

公开(公告)号：EP1560383A2

公开(公告)日：2005-08-03

申请号：EP05447013.3

申请日：2005-01-31

Applicant: STMicroelectronics Belgium N.V.

Inventor： Huylebroeck, Marc

IPC: H04L12/56

CPC classification number: H04W74/06 ,  H04W52/0274 ,  H04W56/00 ,  H04W84/18 ,  Y02D70/144 ,  Y02D70/25

Abstract: A Bluetooth master radio frequency unit (20) addresses a slave radio frequency unit, to enable the slave to synchronize to the master, by sending poll packets and optionally null packets over an active link, the master being arranged so that receipt of a response from the slave unit to a poll packet is sufficient to maintain the active link. The slave unit does not have to respond to all of the poll packets. This approach can allow the slave to preserve more (transmit) power by going into a deep sleep mode in which a low power oscillator may be used while still allowing the master unit to detect whether the slave has resynchronized or not (and thus to update a Link Supervision Timer for example).

Abstract translation: 蓝牙主机射频单元（20）寻址从射频单元，以使从机能够与主机同步，通过在主动链路上发送轮询分组和可选的零分组，主机被安排成从 到轮询分组的从单元足以维持活动链路。 从属单元不必对所有的轮询数据包做出响应。 该方法可以允许从机通过进入深度休眠模式来保持更多（发送）功率，其中可以使用低功率振荡器，同时仍然允许主单元检测从机是否已经重新同步（并且因此来更新 Link监控定时器）。

公开(公告)号：EP1548994A1

公开(公告)日：2005-06-29

申请号：EP03078715.4

申请日：2003-11-26

Applicant: STMicroelectronics Belgium N.V.

Inventor： Van Parys, Jorgen

IPC: H04L12/56

CPC classification number: H04W74/04 ,  H04W74/06 ,  H04W84/18 ,  Y02D70/144

Abstract: A Bluetooth master unit (20) polls a slave unit to enable the slave to resynchronize to the master, by sending POLL packets with sufficient frequency to maintain a connection to the slave, and in the intervals between such packets, sending NULL packets with sufficient frequency to maintain synchronization of the slave. By replacing some POLL packets with NULL packets, since the slave does not have to respond to a NULL packet, it can save some power, and there is reduced interference on other piconets. The frequency of the remaining POLL packets is set according to a Link Supervision Timeout (to avoid this timer expiring and thus keep the Bluetooth Link to the slave alive) and according to the time since the master received the last packet from the slave.

Abstract translation: 蓝牙主机单元（20）轮询从单元以允许从机与主机重新同步，通过发送具有足够频率的POLL分组来维持与从机的连接，并且在这些分组之间的间隔中，以足够的频率发送NULL分组 以保持从站的同步。 通过用NULL数据包替换一些POLL数据包，由于从器件不必响应NULL数据包，因此可以节省一些电力，并减少了对其他微微网的干扰。 剩余的POLL分组的频率根据链路监控超时设置（以避免该定时器到期，从而保持蓝牙链路到从机活动），并根据从主机从从机接收到最后一个分组的时间。

公开(公告)号：EP1503293A3

公开(公告)日：2005-02-23

申请号：EP03079181.8

申请日：2003-12-24

Applicant: STMicroelectronics Belgium N.V.

Inventor： Pisoni, Fabio

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: An M-point Fractional Fourier is described using several 2M-points traditional Fourier transforms. The signal path is fed through a series of blocks including a first multiplier, a zero pad, an FFT 2m, a second multiplier, an IFFT 2M, a 1 st half element, and a third multiplier. The first and third multipliers have as their other inputs a value exp(-jπn 2 α) for n=0:M-1, derived from the clock offset signal represented by α.

公开(公告)号：EP1506653A2

公开(公告)日：2005-02-16

申请号：EP03724678.2

申请日：2003-05-19

Applicant: STMicroelectronics N.V. ,  STMicroelectronics Belgium N.V.

Inventor： PISONI, Fabio ,  HUG, Roland ,  BONAVENTURA, Marco

IPC: H04L27/26

CPC classification number: H04B3/23 ,  H04L25/03012 ,  H04L25/03159 ,  H04L27/2647

Abstract: An equalizer for a multi carrier transmission system, converts a transmitted multi carrier signal into sampled frequency domain signals, and suppresses time domain delay dispersion, on the sampled frequency domain signals. It exploits circulant decomposition of a Toeplitz matrix to enable the computationally heavy evaluation of a matrix multiplied by a vector, to be avoided. Increased precision arises from the frequency domain processing being equivalent to a longer time domain FIR filter than is normally practical. The amount of compensation for different carriers can be adjusted, which can lead to increased precision.

公开(公告)号：EP1469591A1

公开(公告)日：2004-10-20

申请号：EP04447099.5

申请日：2004-04-19

Applicant: STMicroelectronics Belgium N.V.

Inventor： Borremans, Marc

IPC: H03D7/14 ,  H03C1/54

CPC classification number: H03D7/1441 ,  H03C1/547 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/1483 ,  H03D7/1491 ,  H03D2200/0043 ,  H03D2200/0084

Abstract: An up conversion mixer has a Gilbert cell arrangement including an input amplification part (BB) for producing an amplified signal coupled to a multiplication part (RF), the multiplication part being arranged to multiply the amplified signal by a local oscillator signal (LO) and output a mixed signal, the mixer also having a capacitor (90,100,15) coupled from a node between the input amplification part and the multiplication part, to a power supply line, for suppressing unwanted high frequency signal components of the output signal of the multiplication part The linearity of such mixers can be improved considerably by this impedance on the source node of the switch transistors. This capacitance can be placed to either VSS or to VDD Notably this improvement can be achieved with low power consumption since no additional power is needed for the increased performance.

Abstract translation: 升压转换混频器具有吉尔伯特单元布置，其包括用于产生耦合到乘法部分（RF）的放大信号的输入放大部分（BB），乘法部分被布置成将放大的信号乘以本地振荡器信号（LO）和 输出混合信号，所述混频器还具有从输入放大部分和乘法部分之间的节点耦合的电容器（90,100,15）到电源线，用于抑制乘法的输出信号的不需要的高频信号分量 部分这种混频器的线性度可以通过开关晶体管的源极节点上的这种阻抗而大大提高。 该电容可以放置在VSS或VDD中。显然，这种改进可以通过低功耗实现，因为不需要额外的功率来提高性能。

公开(公告)号：EP1434142A1

公开(公告)日：2004-06-30

申请号：EP02447274.8

申请日：2002-12-24

Applicant: STMicroelectronics Belgium N.V.

Inventor： Pisoni, Fabio

IPC: G06F17/14

CPC classification number: G06F17/142 ,  G06F17/141 ,  H03H2017/0214

Abstract: An M-point Fractional Fourier is described using several 2M-points traditional Fourier transforms. The signal path is fed through a series of blocks including a first multiplier, a zero pad, an FFT 2m, a second multiplier, an IFFT 2M, a 1 st half element, and a third multiplier. The first and third multipliers have as their other inputs a value exp(-j n 2 ) for n=0:M-1, derived from the clock offset signal represented by.

Abstract translation: 使用几个2M点传统傅立叶变换来描述M点分数傅里叶。 信号路径通过包括第一乘法器，零焊盘，FFT2m，第二乘法器，IFFT 2M，第一半元件和第三乘法器的一系列块馈送。 对于n = 0：M-1，第一和第三乘法器具有作为其另一个输入的值exp（-j n 2），从由...表示的时钟偏移信号导出。

公开(公告)号：EP1638210B1

公开(公告)日：2009-05-06

申请号：EP04077551.2

申请日：2004-09-15

Applicant: STMicroelectronics Belgium N.V.

Inventor： Borremans, Marc ,  Goetschalckx, Paul ,  Monterastelli, Andrea

IPC: H04B1/04 ,  H03D7/16 ,  H03C3/40

CPC classification number: H03J1/005 ,  H04B2001/0491