公开(公告)号：EP1804159B1

公开(公告)日：2009-12-09

申请号：EP05078050.1

申请日：2005-12-30

Applicant: STMicroelectronics Belgium N.V.

Inventor： Himpe, Vincent

IPC: G06F5/06

CPC classification number: G06F5/06

公开(公告)号：EP1596266A1

公开(公告)日：2005-11-16

申请号：EP04447121.7

申请日：2004-05-14

Applicant: STMicroelectronics Belgium N.V.

Inventor： Himpe, Vincent

IPC: G05F1/56

CPC classification number: G05F1/571

Abstract: The present invention is related to a regulator circuit comprising a regulator circuit input and a regulator circuit output, a regulating element in connection with the regulator circuit input and the regulator circuit output, and a control circuit arranged for being fed with a signal related to the regulator circuit output. The regulator circuit further comprises a safety detector arranged for being fed with the signal related to the regulator circuit output. The safety detector is further arranged to control a switch, being in connection with the control circuit's output and with the regulating element.

Abstract translation: 本发明涉及一种调节器电路，其包括调节器电路输入和调节器电路输出，与调节器电路输入和调节器电路输出相关的调节元件，以及控制电路，被配置为馈送与 稳压电路输出。 调节器电路还包括安全检测器，安全检测器被布置为馈送与调节器电路输出相关的信号。 安全检测器还被布置成控制与控制电路的输出和调节元件相关的开关。

公开(公告)号：EP1804159A1

公开(公告)日：2007-07-04

申请号：EP05078050.1

申请日：2005-12-30

Applicant: STMicroelectronics Belgium N.V.

Inventor： Himpe, Vincent

IPC: G06F5/06

CPC classification number: G06F5/06

Abstract: A serial in random out memory circuit has a number of memory cells (10) integrated with write control circuitry (decoder1, decoder 2, 20) for writing a sequence of data inputs to sequential locations in the memory cells. Read control circuitry (decoder1, decoder 2, 20) is integrated to receive address signals from an external device and provide a random access read output from the memory cells, mapped into an address range of the external device. Compared to circuits using discrete components and conventional RAM chips, the integrated SIRO can enable some of the circuitry or external software to be dispensed with and so reduce costs or increase performance. The memory cells can be arranged in a number of blocks, selectable one at a time for mapping to the external device address range.

Abstract translation: 串行随机输出存储器电路具有与写入控制电路（解码器1，解码器2,20）集成的多个存储器单元（10），用于将数据输入序列写入存储器单元中的顺序位置。 读取控制电路（解码器1，解码器2,20）被集成以从外部设备接收地址信号，并且提供映射到外部设备的地址范围的来自存储器单元的随机存取读取输出。 与使用分立元件和常规RAM芯片的电路相比，集成SIRO可以使部分电路或外部软件得以免除，从而降低成本或提高性能。 存储器单元可以被布置在多个块中，一次可选地用于映射到外部设备地址范围。