公开(公告)号：GB201809979D0

公开(公告)日：2018-08-01

申请号：GB201809979

申请日：2012-06-16

Applicant: TENSORCOM INC

Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

公开(公告)号：AU2016358191A1

公开(公告)日：2018-05-31

申请号：AU2016358191

申请日：2016-11-16

Applicant: TENSORCOM INC

Inventor： SOE ZAW ,  JING KEVIN ,  GAO STEVE

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：IL229935A

公开(公告)日：2018-02-28

申请号：IL22993513

申请日：2013-12-17

Applicant: TENSORCOM INC

Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

公开(公告)号：CA3005740A1

公开(公告)日：2017-05-26

申请号：CA3005740

申请日：2016-11-16

Applicant: TENSORCOM INC

Inventor： SOE ZAW ,  JING KEVIN ,  GAO STEVE

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：DE112012002508T5

公开(公告)日：2014-06-12

申请号：DE112012002508

申请日：2012-06-16

Applicant: TENSORCOM INC

Inventor： THAM KONG-MENG ,  SOE ZAW

IPC: H04B7/00

Abstract: Die vorliegende Erfindung beseitigt die Notwendigkeit einer ”Kondensatorkopplung” oder ”Transformatorkopplung” und die entsprechende unerwünschte parasitäre Kapazität und Induktivität, die mit diesen Kopplungstechniken bei der Gestaltung von Hochfrequenzschaltungen (~60 GHz) verbunden sind. Bei dieser Frequenz muss der Abstand zwischen zwei benachbarten Stufen minimiert werden. Eine Resonanzschaltung in Serie mit der Stromzufuhr- oder Masseleitung wird verwendet, um ein Vorspannsignal von einem Hochfrequenzsignal zu isolieren. Die Einführung dieser Resonanzschaltung ermöglicht ein ”direktes Koppeln” einer ersten Stufe an eine nächste Stufe mit einer metallischen Leiterbahn. Bei der Technik der ”direkten Kopplung” wird sowohl das Hochfrequenzsignal als auch die Vorspannung an die nächste Stufe übergeben. Im Vergleich zum Ansatz der ”Wechselstromkopplung” oder ”Transformatorkopplung” überwindet der Ansatz der ”direkten Kopplung” das Problem des Verbrauchs großer Chipflächen, da zum Übertragen der Hochfrequenzsignale zwischen den Stufen weder Kondensatoren noch Transformatoren erforderlich sind.

公开(公告)号：WO2013043957A3

公开(公告)日：2014-05-08

申请号：PCT/US2012056466

申请日：2012-09-21

Applicant: TENSORCOM INC

Inventor： SOE ZAW

IPC: H01L23/52 ,  H01L27/02

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

Abstract translation: 超高频电路遭受寄生电阻。 在60GHz时，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的门之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 另外，使用通孔堆叠的抽头来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：WO2014036542A1

公开(公告)日：2014-03-06

申请号：PCT/US2013/057758

申请日：2013-09-02

Applicant: TENSORCOM, INC.

Inventor： DAI, Dai

IPC: H03F3/45

CPC classification number: H03M1/0818 ,  H03M1/0809 ,  H03M1/124 ,  H03M1/365

Abstract: The core concept of this ADC is the high-speed fully-differential comparators which are clocked at 2.64 GHz and used in a 60 GHz transceiver. The comparator consists of a pre-amplifier stage, a capture stage, a regeneration cell and an output latch. The pre-amplifier stage is not clocked; therefore, the pre-amplifier stage does not suffer initialization and transient behavior effects when the clock signal switches state. The transient response of being enabled and disabled is eliminated. Instead, a capture stage transfers the contents of the pre-amplifier stage into a memory regeneration stage. The capture stage is clocked by pulses that are timed to minimize the clock kick-back generated by the memory regeneration stage. The clock kick-back is reduced even when many comparators are coupled to the PGA. The comparators are also aligned right next to each other to minimize the mismatching layout effect.

Abstract translation: 该ADC的核心概念是高速全差分比较器，时钟频率为2.64 GHz，用于60 GHz收发器。 比较器由前置放大器级，捕获级，再生单元和输出锁存器构成。 前置放大器级没有计时; 因此，当时钟信号切换状态时，前置放大器级不会受到初始化和瞬态特性的影响。 消除了启用和禁用的瞬态响应。 相反，捕获级将前置放大器级的内容传送到存储器再生级。 捕获级由定时的脉冲计时，以最小化由存储器再生阶段产生的时钟反冲。 即使许多比较器耦合到PGA，时钟反转也减少。 比较器也彼此对齐，以最小化不匹配的布局效果。

公开(公告)号：WO2014025714A1

公开(公告)日：2014-02-13

申请号：PCT/US2013/053681

申请日：2013-08-06

Applicant: TENSORCOM, INC.

Inventor： CHEN, Jiashu

IPC: H04B1/04 ,  H04B1/16

CPC classification number: G06F1/10 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H04B7/0617 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/22 ,  Y02D70/444

Abstract: The class-E amplifier can be tuned to pass only the fundamental frequency to the antenna by optimizing the second harmonics at the drain of the final PA driver transistor. A CPW in series with a capacitor between the PA transistor and the load forms a band pass filter that only allows the fundamental frequency to pass to the load of the antenna. A supply inductor to couple the drain of the final PA driver transistor to the power supply is tuned at the second harmonic with the parasitic capacitance of the drain of the PA transistor. A load capacitance is adjusted at the fundamental frequency to insure that the current waveform and voltage waveforms at the drain of the PA driver transistor do not overlap, thereby minimizing the parasitic power dissipation and allowing maximum energy to be applied to the antenna.

Abstract translation: 可以通过优化最终PA驱动器晶体管的漏极处的二次谐波，将E类放大器调谐为仅将基频通过天线。 与PA晶体管和负载之间的电容器串联的CPW形成只允许基频通过天线负载的带通滤波器。 将最终PA驱动器晶体管的漏极耦合到电源的电源电感器被调谐在具有PA晶体管的漏极的寄生电容的二次谐波处。 负载电容被调整到基频，以确保PA驱动晶体管的漏极处的电流波形和电压波形不重叠，从而最小化寄生功率耗散，并允许最大的能量施加于天线。

公开(公告)号：WO2013043954A3

公开(公告)日：2013-06-06

申请号：PCT/US2012056463

申请日：2012-09-21

Applicant: TENSORCOM INC

Inventor： SOE ZAW

IPC: H03L7/06

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract translation: 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。 其中一个难题是使用传统CMOS将高频时钟分频为可管理的时钟频率。 虽然注入锁定分频器可以分解这个时钟频率，但这些分频器有局限性。 除以2表示使用几种技术; 前馈，时钟放大和串联峰值电感来克服这些限制。

公开(公告)号：WO2011153291A2

公开(公告)日：2011-12-08

申请号：PCT/US2011038829

申请日：2011-06-01

Applicant: TENSORCOM INC ,  LAKKIS ISMAIL ,  LAW HOCK

Inventor： LAKKIS ISMAIL ,  LAW HOCK

IPC: G01S5/02 ,  G01S11/08 ,  H04W64/00

CPC classification number: H04L27/00 ,  G01S1/20 ,  G01S5/0226 ,  G01S5/0289 ,  G01S5/10 ,  H04B1/69

Abstract: A positioning system comprises a plurality of controllers, each controller comprising a wideband receiver and a narrow band transmitter, the each controller configured to receive a wideband positioning frame using the wideband receiver from one or more devices and to transmit acknowledgement frames using the narrow band transmitter that include timing and control data for use by the devices to establish timing for transmission of the positioning frame; and at least one device comprising a wideband transmitter and a narrow band receiver, the device configured to transmit a positioning frame to the plurality of controllers using the wideband transmitter and to receive an acknowledgement frame from one or more controllers using the narrow band receiver, extract timing and control information from the frame, and adjust the timing and synchronization of the wideband transmitter using the timing and control information.

Abstract translation: 定位系统包括多个控制器，每个控制器包括宽带接收机和窄带发射机，每个控制器被配置为使用来自一个或多个设备的宽带接收机接收宽带定位帧，并使用窄带发射机发送确认帧 其包括由设备使用以建立定位框架的传输定时的定时和控制数据; 以及包括宽带发射机和窄带接收机的至少一个设备，所述设备被配置为使用所述宽带发射机向所述多个控制器发送定位帧并且使用所述窄带接收机从一个或多个控制器接收确认帧，提取 来自帧的定时和控制信息，并且使用定时和控制信息来调整宽带发射机的定时和同步。