公开(公告)号：CA2838967A1

公开(公告)日：2012-12-20

申请号：CA2838967

申请日：2012-06-16

Applicant: TENSORCOM INC

Inventor： THAM KHONGMENG ,  SOE ZAW

IPC: H04B7/00

Abstract: This invention eliminates the need for "capacitor coupling" or "transformer coupling," and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (~60GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be "directly coupled" to a next stage using a metallic trace. The "direct coupling" technique passes both the high frequency signal and the biasing voltage to the next stage. The "direct coupling" approach overcomes the large die area usage when compared to either the "AC coupling" or "transformer coupling" approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

公开(公告)号：DE112012003966T5

公开(公告)日：2014-09-18

申请号：DE112012003966

申请日：2012-09-21

Applicant: TENSORCOM INC

Inventor： SOE ZAW

IPC: H03L7/06

Abstract: Ein Phasenregelkreis (PLL) ist eine wichtige Komponente in drahtlosen Systemen. Die CMOS-Technologie bietet spannungsgesteuerte Oszillatordesigns, die bei 60 GHz arbeiten. Eine der Schwierigkeiten ist die Teilung des Hochfrequenztakts auf eine handhabbare Taktfrequenz unter Verwendung eines herkömmlichen CMOS. Obwohl Injection-Locked-Teiler diese Taktfrequenz teilen können, haben diese Teiler Einschränkungen. Es wird ein Zweiteiler präsentiert, der zur Überwindung dieser Einschränkungen mehrere Techniken verwendet; Vorsteuerung, Taktverstärkung und Reihen-Entzerrspulen.

公开(公告)号：AU2021202432A1

公开(公告)日：2021-05-13

申请号：AU2021202432

申请日：2021-04-21

Applicant: TENSORCOM INC

Inventor： SOE ZAW ,  JING KEVIN ,  GAO STEVE

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

Abstract: Abstract A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：HK1258162A1

公开(公告)日：2019-11-08

申请号：HK19100517

申请日：2019-01-14

Applicant: TENSORCOM INC

Inventor： SOE ZAW ,  JING KEVIN ,  GAO STEVE

IPC: H03G20060101 ,  H03F20060101 ,  H03H20060101

公开(公告)号：AU2016358191A1

公开(公告)日：2018-05-31

申请号：AU2016358191

申请日：2016-11-16

Applicant: TENSORCOM INC

Inventor： SOE ZAW ,  JING KEVIN ,  GAO STEVE

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：CA3005740A1

公开(公告)日：2017-05-26

申请号：CA3005740

申请日：2016-11-16

Applicant: TENSORCOM INC

Inventor： SOE ZAW ,  JING KEVIN ,  GAO STEVE

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：DE112012002508T5

公开(公告)日：2014-06-12

申请号：DE112012002508

申请日：2012-06-16

Applicant: TENSORCOM INC

Inventor： THAM KONG-MENG ,  SOE ZAW

IPC: H04B7/00

Abstract: Die vorliegende Erfindung beseitigt die Notwendigkeit einer ”Kondensatorkopplung” oder ”Transformatorkopplung” und die entsprechende unerwünschte parasitäre Kapazität und Induktivität, die mit diesen Kopplungstechniken bei der Gestaltung von Hochfrequenzschaltungen (~60 GHz) verbunden sind. Bei dieser Frequenz muss der Abstand zwischen zwei benachbarten Stufen minimiert werden. Eine Resonanzschaltung in Serie mit der Stromzufuhr- oder Masseleitung wird verwendet, um ein Vorspannsignal von einem Hochfrequenzsignal zu isolieren. Die Einführung dieser Resonanzschaltung ermöglicht ein ”direktes Koppeln” einer ersten Stufe an eine nächste Stufe mit einer metallischen Leiterbahn. Bei der Technik der ”direkten Kopplung” wird sowohl das Hochfrequenzsignal als auch die Vorspannung an die nächste Stufe übergeben. Im Vergleich zum Ansatz der ”Wechselstromkopplung” oder ”Transformatorkopplung” überwindet der Ansatz der ”direkten Kopplung” das Problem des Verbrauchs großer Chipflächen, da zum Übertragen der Hochfrequenzsignale zwischen den Stufen weder Kondensatoren noch Transformatoren erforderlich sind.

公开(公告)号：WO2013043954A4

公开(公告)日：2013-07-04

申请号：PCT/US2012056463

申请日：2012-09-21

Applicant: TENSORCOM INC

Inventor： SOE ZAW

IPC: H03L7/06

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract translation: 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供了在60 GHz工作的压控振荡器设计。 其中一个困难是使用传统的CMOS将高频时钟降低到可管理的时钟频率。 虽然注入锁定分频器可以分频此时钟频率，但这些分频器有局限性。 提出了使用几种技术的除以2。 前馈，时钟放大和串联峰值电感，以克服这些限制。

公开(公告)号：WO2013043957A3

公开(公告)日：2014-05-08

申请号：PCT/US2012056466

申请日：2012-09-21

Applicant: TENSORCOM INC

Inventor： SOE ZAW

IPC: H01L23/52 ,  H01L27/02

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

Abstract translation: 超高频电路遭受寄生电阻。 在60GHz时，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的门之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 另外，使用通孔堆叠的抽头来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：WO2013043954A3

公开(公告)日：2013-06-06

申请号：PCT/US2012056463

申请日：2012-09-21

Applicant: TENSORCOM INC

Inventor： SOE ZAW

IPC: H03L7/06

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract translation: 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。 其中一个难题是使用传统CMOS将高频时钟分频为可管理的时钟频率。 虽然注入锁定分频器可以分解这个时钟频率，但这些分频器有局限性。 除以2表示使用几种技术; 前馈，时钟放大和串联峰值电感来克服这些限制。