公开(公告)号：JPS631114A

公开(公告)日：1988-01-06

申请号：JP7574287

申请日：1987-03-28

Applicant: XILINX INC

Inventor： UIRIAMU ESU KAATAA

IPC: H03K19/173

公开(公告)号：JPS62142416A

公开(公告)日：1987-06-25

申请号：JP21986086

申请日：1986-09-19

Applicant: XILINX INC

Inventor： HSIEH HUNG-CHENG

IPC: H03K3/3565 ,  H03K19/0185 ,  H03K19/0948

公开(公告)号：JPS61280120A

公开(公告)日：1986-12-10

申请号：JP12135785

申请日：1985-06-04

Applicant: XILINX INC

Inventor： ROSU EICHI FURIIMAN

IPC: H03K19/173

公开(公告)号：JPS61224520A

公开(公告)日：1986-10-06

申请号：JP3060886

申请日：1986-02-14

Applicant: XILINX INC

Inventor： UIRIAMU ESU KAATAA

IPC: G11C19/28 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/173

公开(公告)号：JP2009153171A

公开(公告)日：2009-07-09

申请号：JP2009028638

申请日：2009-02-10

Applicant: Xilinx Inc ,  ザイリンクス インコーポレイテッドXilinx Incorporated

Inventor： LESEA AUSTIN H

IPC: G11C11/41 ,  H03K3/356 ,  G11C11/412 ,  H03K19/0948 ,  H03K19/173

CPC classification number: G11C11/4125

Abstract: PROBLEM TO BE SOLVED: To provide memory cells enhanced for resistance to single event upsets.
SOLUTION: Separate transistors 163, 164 are placed between output of one inverter 161 and gates of PMOS and NMOS transistors of the other inverter 162, these transistors 163, 164 can be separately controlled. An NMOS transistor is placed in a path to the gate of the NMOS transistor of the inverter 162, and a PMOS transistor is placed in a path to the gate of the PMOS transistor of the inverter 162.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供增强的抗单个事件扰乱的存储单元。 解决方案：单独的晶体管163,164被放置在一个反相器161的输出和另一个反相器162的PMOS和NMOS晶体管的栅极之间，这些晶体管163,164可以被单独控制。 NMOS晶体管被放置在到反相器162的NMOS晶体管的栅极的路径中，并且PMOS晶体管被放置在到逆变器162的PMOS晶体管的栅极的路径中。版权所有（C）2009 ，JPO＆INPIT

公开(公告)号：JP2009060676A

公开(公告)日：2009-03-19

申请号：JP2008321296

申请日：2008-12-17

Applicant: Xilinx Inc ,  ザイリンクス インコーポレイテッドXilinx Incorporated

Inventor： NGUYEN HY V ,  HUANG GUBO ,  NGUYEN ANDY T

IPC: H03K17/04 ,  H03K19/0175 ,  H03K17/687 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185

CPC classification number: H03K19/01721 ,  H03K19/00315

Abstract: PROBLEM TO BE SOLVED: To provide an output circuit which can receive an input signal in one voltage level (e.g. in the lower voltage level) and can provide an output signal in another voltage level (e.g. in the higher voltage level) to maintain high operation speed.
SOLUTION: The output circuit provides compatibility with various input and output voltage levels without compromising its capability. A pull-up (P12) on an output terminal is gated by an internal node (PD), and the invention encompasses various circuits and means for supplying a data input signal to this internal node (PD). One embodiment includes a level shifter (100) on the data input path, and also provides an alternative path that bypasses the level shifter and runs through the output circuit. When the input data value goes high, the alternative path quickly supplies an attenuated high value to the internal node. Then the level shifter is activated and increases the internal node voltage to the output power high level, ensuring that the output pull-up (P12) is completely off.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够接收一个电压电平（例如在较低电压电平）中的输入信号的输出电路，并且可以将另一个电压电平（例如，较高电压电平）的输出信号提供给 保持高运行速度。

解决方案：输出电路提供与各种输入和输出电压电平的兼容性，而不会影响其性能。 输出端子上的上拉（P12）由内部节点（PD）选通，本发明包括用于向该内部节点（PD）提供数据输入信号的各种电路和装置。 一个实施例在数据输入路径上包括电平移位器（100），并且还提供旁路电平移位器并穿过输出电路的替代路径。 当输入数据值变高时，替代路径快速向内部节点提供衰减的高值。 然后电平移位器被激活，并将内部节点电压增加到输出功率高电平，确保输出上拉（P12）完全关闭。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPH08265136A

公开(公告)日：1996-10-11

申请号：JP34328295

申请日：1995-12-28

Applicant: XILINX INC

Inventor： KERII EMU PIASU ,  CHIYAARUZU AARU ERITSUKUSON ,  CHII-TSUN FUAN ,  DAGURASU PII UIIRANDO

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

Abstract: PROBLEM TO BE SOLVED: To minimize the generation of delay by providing plural programmable interconnection points PIPs and programming the respective PIPs so as to connect one of output lines to one of input lines. SOLUTION: A PIP array TA11 in a tile T11 is provided with the programmable interconnection points PIPs P111-P114. The output line 04 of the tile T21 is programmed to the input line 14 of the tile P22 through the programmable interconnection point P221. Thus, connection is made possible by being programmed to the input line 14 of the tile T12 through the connectable and programmable interconnection point P224. Thus, the output line 04 accesses the two PIPs and the output line 05 accesses the two PIPs further. For instance, the output line 05 in the T21 accesses the connection point P222 in the tile T22 and accesses the programmable connection point P233 in the tile T23.

公开(公告)号：JPH08107347A

公开(公告)日：1996-04-23

申请号：JP12125195

申请日：1995-05-19

Applicant: XILINX INC

Inventor： ROSU EICHI FURIIMAN

IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

Abstract: PURPOSE: To provide an interconnection structure for an integrated circuit which has flexibility and high efficiency. CONSTITUTION: An interconnection structure which programmably interconnects wiring in an integrated circuit has a connection programmable means which has at least three sets of interconnection lines that contain 1st, 2nd and 3rd sets, connects at least one wiring in the 1st set to at least one of distributions in the 2nd set, connects at least one wiring in the 1st set to at least one of wiring in the 3rd set, and also connects at least one wiring in the 2nd set to at least one of wiring in the 3rd set.

公开(公告)号：JPH07159498A

公开(公告)日：1995-06-23

申请号：JP11778193

申请日：1993-04-20

Applicant: XILINX INC

Inventor： EFU ERITSUKU GETEINGU

IPC: G01R31/317 ,  H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To determine whether all the produced elements are good or defective by providing a configuration control unit, which is connected to an inverter inside another configuration control unit and is provided with a means loading a signal on a connection line corresponding to the inverter. CONSTITUTION: A configuration control unit(CCU) is provided with a pair of inverters INV 1, 2 which turn on transistors(Tr) 805, 806 on the basis of a high logic signal PHI, PHIH and turn off transistors Tr 801, 802 on the basis of low logic signal PHB, PHIC so as to be connected to each other as a latch. A circuit 810 controlling impression of programming voltage VP to a corresponding signal I is provided with a transistor Tr 813 supplying the voltage VP to the signal I and controlling means (ENA, Tr 811, Tr 812) for the transistor Tr 813. In this way, the transistor Tr 813 supplies the programming voltage VP to the corresponding signal I when the stored signal Q equals a selected voltage (high) and the means (ENA, Tr 811, Tr 812) select the stored value.

公开(公告)号：JPH0574949A

公开(公告)日：1993-03-26

申请号：JP34819391

申请日：1991-12-04

Applicant: XILINX INC

Inventor： DEBITSUTO BII PAARAA ,  EFU ERITSUKU GOUCHINGU

IPC: G06F11/22 ,  G01R27/02 ,  G01R31/30 ,  G01R31/3185 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: PURPOSE: To provide an integrated circuit chip, to be programmed by a customer by using an anti-fuse with the anti-fuse test structure which has characteristics similar to those of the part of the integrated circuit. CONSTITUTION: In order to test the speed and ease of programming of a user programmable chip 101 and the resistance of the anti-fuse, a test structure having an anti-fuse which has been programmed in a test prior to shipment is arranged at its peripheral part. Anti-fuse units 1101 to 1124 are composed of programmed anti-fuses and logic circuits. Signals, which propagate along test paths are switched at the same speed as a maximum permissible time delay to test propagation time delays to determine whether or not the signals can be propagated through the test paths within a specific time before the signals, are switched.