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    PROGRAMMABLE LOGIC DEVICE
    1.
    发明专利
    PROGRAMMABLE LOGIC DEVICE 失效

    公开(公告)号：JPH09261040A

    公开(公告)日：1997-10-03

    申请号：JP26214696

    申请日：1996-10-02

    Applicant: XILINX INC

    Inventor： UIRIAMU ESU KAATAA ,  ROSU EICHI FURIIMAN

    IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

    Abstract: PROBLEM TO BE SOLVED: To provide a programmable logic circuit formed on an integrated circuit chip in which a desired logic function is realized easily by the user through programming. SOLUTION: This logic device is provided with plural logic elements LEs each of which has an input lead (in) and an output lead (out), and a desired logic form is set to each logic element to realize a desired logic function. A group of interconnection lines L interconnecting the logic elements are provided and plural input/output ports I/O are provided. A programmable connection means is provided to allow a group of the interconnection lines to be mutually connected, to allow a group of the interconnection lines to be connected to input leads or output leads of selected logic elements and to allow a group of interconnection lines to be selectively connected to input/output ports through programming.

    PROGRAMMABLE LOGICAL DEVICE
    6.
    发明专利
    PROGRAMMABLE LOGICAL DEVICE 失效

    公开(公告)号：JPH09261039A

    公开(公告)日：1997-10-03

    申请号：JP26212796

    申请日：1996-10-02

    Applicant: XILINX INC

    Inventor： UIRIAMU ESU KAATAA ,  ROSU EICHI FURIIMAN

    IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

    Abstract: PROBLEM TO BE SOLVED: To allow a user to easily program, so as to realize a desired logical function by providing a means connecting input and output leads to mutual connection lines by respective programming and a means mutually connecting the mutual connecting lines by programming. SOLUTION: Each CLE of nine CLEs 40-1 to 40-9 is provided with plural input leads and not less than one output lead. Each input lead is provided with plural access connection parts and each of them connects a selected general connection lead to an input lead. These logical elements 40-1 to 40-9 are arranged on an integrated circuit chip with a general mutual connection constituting body provided with a programmable access connection part and a programmable general mutual connection part for connecting a general mutual connection lead and various leads to another lead. Then an electrical path from the output lead of one CLE to the input lead of another CLE involves the general mutual connection part.

    SINGLE CHIP PATTERN ADAPTABLE LOGIC ARRAY
    7.
    发明专利
    SINGLE CHIP PATTERN ADAPTABLE LOGIC ARRAY 失效

    公开(公告)号：JPH08204543A

    公开(公告)日：1996-08-09

    申请号：JP12105895

    申请日：1995-05-19

    Applicant: XILINX INC

    Inventor： UIRIAMU ESU KAATAA ,  ROSU EICHI FURIIMAN

    IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

    Abstract: PURPOSE: To reduce the whole size of a general interconnection structure and an array by providing a special interconnection circuit. CONSTITUTION: A special vertical lead circuit SVC is provided with a special interconnection circuit S1 connected to output leads 1 and programmable access connecting sections P1-P4 and P5-P8 which connect the circuit S1 to desired input leads of morphology adaptive logic arrays (CLEs) 9-1 and 9-3. Similarly, a special horizontal lead circuit SHC is provided with a special interconnection circuit S2 connected to the output lead 2 of the CLE 9-3 and programmable access connecting sections P9-P12 which connect the lead 2 to the desired input lead of a CLE 9-4 and can be programmed to the connecting section of an ordinary connecting structure. Since the circuits S1 and S2 are provided in such a way, the number of ordinary interconnection leads and connecting sections can be reduced from the CLEs and, in addition, the signal speed can be improved through the circuits S1 and S2.

    MEMORY CIRCUIT PROVIDED WITH CHANGEABLE CONSTITUTION
    8.
    发明专利
    MEMORY CIRCUIT PROVIDED WITH CHANGEABLE CONSTITUTION 失效

    公开(公告)号：JPH0645912A

    公开(公告)日：1994-02-18

    申请号：JP29052891

    申请日：1991-10-09

    Applicant: XILINX INC

    Inventor： UIRIAMU ESU KAATAA

    IPC: G11C19/28 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/173

    Abstract: PURPOSE: To configure a configurable logic element which realizes extremely diversified functions. CONSTITUTION: A combination logic circuit receives N-sets of binary input signals, fed to a configurable logic element 99 and M-sets of binary feedback signals from a storage circuit 120. A combination logic circuit 100 is configured to have a plurality of configurations. Each configuration realizes one or a plurality of selected combination logic functions as partial sets, which is selected from one or a plurality of input signals to the combination logic circuit. Since the combination logic circuit 100 is configurable, the circuit 100 is used to realize a plurality of different functions. Furthermore, two functions or over are realized simultaneously, and they can be made to appeared on different output leads of the configurable logic element 100.

    PROGRAMMBLE CONNECTOR AND CONTROL STRUCTURE OF STATE OF CONNECTION LINE IN PROGRAMMABLE CIRCUIT
    9.
    发明专利
    PROGRAMMBLE CONNECTOR AND CONTROL STRUCTURE OF STATE OF CONNECTION LINE IN PROGRAMMABLE CIRCUIT 失效

    公开(公告)号：JPH04223715A

    公开(公告)日：1992-08-13

    申请号：JP8789491

    申请日：1991-03-27

    Applicant: XILINX INC

    Inventor： ROSU EICHI FURIIMAN ,  KIYUU DOUONGU ,  HANGUUCHIENGU SHII ,  CHIYAARUZU AARU ERIKUSON ,  UIRIAMU ESU KAATAA

    IPC: G06F3/00 ,  H01L21/82 ,  H03K19/173

    Abstract: PURPOSE: To provide a structure effective for a configurable logic array having plural conductive connecting lines around it to prevent the speed of information processing from being decelerated and valuable resources inside a chip usable for executing a complicated function from being used. CONSTITUTION: A line running from a pin or a pad outside a programmable connection circuit is used for controlling a signal to be impressed to the connecting line. Concerning this signal and its complement, the application of a voltage to be supplied to the connecting line is controlled while using a programmable connection part. When the 2nd supply voltage is applied through a resistor to the connecting line, the connecting line transmits a logic signal expressing the logic function such as AND, for example, of the set of selected input signals or their complements. Besides, a line inside a configurable logic array chip is effective for a signal generated on the connecting line. Because of a bidirectional programmable connection circuit, an input pin can be functioned as the input pin or as an output pin. This structure can be used as the latch of a data/address demultiplexer and applied to a decoder circuit.

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