公开(公告)号：KR1020130017647A

公开(公告)日：2013-02-20

申请号：KR1020110080214

申请日：2011-08-11

Applicant: 삼성전자주식회사

Inventor： 남경태 ,  김기준 ,  황영남

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76897 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/04

Abstract: PURPOSE: A method for manufacturing a variable resistance memory device is provided to improve the integration of a semiconductor device by supplying a source line pattern used for a common source line of adjacent gates. CONSTITUTION: A device isolation layer(101) is formed on a substrate. First source and drain regions are formed between gate line structures(GL) and conductive separation patterns(Cl). Second source and drain regions are formed between the gate line structures. The gate line structures are buried in the substrate by interposing the first source and drain regions. Bottom contact plugs are formed on the first source and drain regions. Variable resistance structures are electrically connected to the first source and drain regions through the bottom contact plugs.

Abstract translation: 目的：提供一种用于制造可变电阻存储器件的方法，通过提供用于相邻栅极的公共源极线的源极线图案来改善半导体器件的集成。 构成：在基板上形成器件隔离层（101）。 在栅极线结构（GL）和导电分离图案（Cl）之间形成第一源区和漏区。 第二源极和漏极区域形成在栅极线结构之间。 栅极线结构通过插入第一源极和漏极区域而被掩埋在衬底中。 底部接触塞形成在第一源区和漏区上。 可变电阻结构通过底部接触插塞电连接到第一源极和漏极区域。

公开(公告)号：KR1020090075539A

公开(公告)日：2009-07-08

申请号：KR1020080001431

申请日：2008-01-04

Applicant: 삼성전자주식회사

Inventor： 이태연 ,  김기준 ,  이준호 ,  김철규

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/148 ,  G11C13/0004

Abstract: A phase change random access memory composed with a single element semi-metal film is provided to realize a phase change memory having higher wiring speed than a conventional GST(Ge-Sb-Te) material by providing the semi-metal film between the bottom electrode and the top electrode. In a phase change random access memory, a storage node comprises a phase change material layer(12). In a storage node, a semi-metal film of a single group is formed between the top electrode and the bottom electrode. The semi-metal thin film is made of Sb or Bi, and the thickness of the semi-metal thin film is 0.1nm - 15nm. More than one of nitrogen, oxygen, carbon, boron, and mixture of them is doped to the semi-metal of a single group. The oxygen and nitrogen are doped in the semi-metal film of a single group.

Abstract translation: 提供了由单元件半金属膜构成的相变随机存取存储器，以通过在半导体器件的底部电极之间提供半金属膜来实现具有比常规GST（Ge-Sb-Te）材料更高布线速度的相变存储器 和顶部电极。 在相变随机存取存储器中，存储节点包括相变材料层（12）。 在存储节点中，在顶电极和底电极之间形成单组半金属膜。 半金属薄膜由Sb或Bi制成，半金属薄膜的厚度为0.1nm〜15nm。 氮，氧，碳，硼及其混合物中的一种以上掺杂到单组分的半金属中。 氧和氮掺杂在单组的半金属膜中。

公开(公告)号：KR1020090043922A

公开(公告)日：2009-05-07

申请号：KR1020070109730

申请日：2007-10-30

Applicant: 삼성전자주식회사

Inventor： 김기준

IPC: H01L27/115

CPC classification number: H01L45/06 ,  H01L21/31051 ,  H01L45/1233 ,  H01L45/141

Abstract: 본 발명은 상변화 메모리 소자에 관한 것이다. 본 발명에서는, 스위치 영역과 연결된 하부 전극 콘택층; 상기 하부 전극 콘택층 상에 형성된 상변화층; 상기 상변화층을 둘러싸며 형성된 절연층; 및 상기 상변화층 및 상기 절연층 사이에 형성된 중간층;을 포함하는 상변화 메모리 소자를 제공한다.

公开(公告)号：KR1020080064605A

公开(公告)日：2008-07-09

申请号：KR1020070001696

申请日：2007-01-05

Applicant: 삼성전자주식회사

Inventor： 신웅철 ,  김기준 ,  허지현 ,  이효석

IPC: H01L27/115

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683 ,  G11C13/0004

Abstract: A phase change memory device and a method for manufacturing the same are provided to prevent degradation in a boundary between a BEC(Back Electrode Contact) and a phase change layer using a phase change layer as the BEC thereof. A phase change memory device includes a lower electrode, a BEC(23), a first phase change layer, a second phase change layer, and an upper electrode(26). The BEC is formed on the lower electrode by using phase change materials. The first phase change layer is formed on the BEC, and has a width less than that of the BEC. The second phase change layer is formed on the first phase change layer, and has a width greater than that of the first phase change layer. The upper electrode is formed on the second phase change layer. A first insulation layer is formed on a lateral surface of the lower electrode and a side of the BEC. A second insulation layer is formed on a lateral surface of the first phase change layer.

Abstract translation: 提供了一种相变存储器件及其制造方法，以防止使用相变层作为其BEC的BEC（背极接触）和相变层之间的边界的劣化。 相变存储器件包括下电极，BEC（23），第一相变层，第二相变层和上电极（26）。 BEC通过使用相变材料形成在下电极上。 第一相变层形成在BEC上，其宽度小于BEC的宽度。 第二相变层形成在第一相变层上，其宽度大于第一相变层的宽度。 上电极形成在第二相变层上。 第一绝缘层形成在下电极的侧表面和BEC侧。 第二绝缘层形成在第一相变层的侧表面上。

公开(公告)号：KR1020070087869A

公开(公告)日：2007-08-29

申请号：KR1020060001392

申请日：2006-01-05

Applicant: 삼성전자주식회사

Inventor： 노진서 ,  김기준 ,  강윤호

IPC: H01L27/115

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

Abstract: A phase changing material, a phase changing memory comprising the same, and a method for operating the same are provided to reduce the size of a transistor and to increase the level of integration of PRAM(Phase changing Random Access Memory) by lowering reset current. A phase changing memory includes a switching element and a storage node connected to the switching element. The storage node includes a first electrode(52), a phase changing layer(60), and a second electrode(62). The phase changing layer is formed by doping Ge into an InSbTe compound. The Ge of the phase changing layer is equal to or less than 10 atom percent. The InSbTe compound is formed with In of 20 to 50 atom percent, Sb of 10 to 20 atom percent, and Te of 30 to 55 atom percent.

Abstract translation: 提供相变材料，包括该相变材料的相变存储器及其操作方法，以减小晶体管的尺寸并通过降低复位电流来增加PRAM（相变随机存取存储器）的集成度。 相变存储器包括开关元件和连接到开关元件的存储节点。 存储节点包括第一电极（52），相变层（60）和第二电极（62）。 相变层通过将Ge掺杂入InSbTe化合物而形成。 相变层的Ge等于或小于10原子％。 InSbTe化合物由20〜50原子％的In，10〜20原子％的Sb，30〜55原子％的Te构成。

公开(公告)号：KR1020030065699A

公开(公告)日：2003-08-09

申请号：KR1020020005420

申请日：2002-01-30

Applicant: 삼성전자주식회사

Inventor： 김기준

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0248 ,  G09G2330/023

Abstract: PURPOSE: An output circuit of a source driver for TFT LCD is provided to improve a slow-rate of an input signal of a source driver to a panel and reduce the power consumption of a source driver by using the first and the second voltages and the first and the second external voltages. CONSTITUTION: An output circuit of a source driver for TFT LCD includes the first to the n-th voltage generation units(410-414), the first to the n-th switch units(SW1-SWn), the first to the n-th sub switch units(SWS1-SWSn), and a voltage generation unit(420). The voltage generation units are used for receiving the first to the n-th input voltages and generating the first to the n-th sub input voltages. The first to the n-th switch units are used for generating the first to the n-th output voltages corresponding to the first to the n-th sub input voltages. The first to the n-th sub switch units are used for connecting or disconnecting predetermined share lines to or from the first to the n-th output voltages. The voltage generation unit is used for receiving the first and the second voltages and applying the predetermined precharge voltages to the share lines.

Abstract translation: 目的：提供用于TFT LCD的源极驱动器的输出电路，以改善源极驱动器对面板的输入信号的慢速率，并通过使用第一和第二电压降低源极驱动器的功耗，并且 第一和第二外部电压。 构成：用于TFT LCD的源极驱动器的输出电路包括第一至第n电压产生单元（410-414），第一至第n开关单元（SW1-SWn），第一至第n- （SWS1-SWSn）和电压产生单元（420）。 电压产生单元用于接收第一至第n输入电压并产生第一至第n子输入电压。 第一到第n开关单元用于产生对应于第一至第n子输入电压的第一至第n输出电压。 第一到第n子开关单元用于将预定的共享线路连接到或从第一至第n输出电压断开。 电压产生单元用于接收第一和第二电压，并将预定的预充电电压施加到共享线。

公开(公告)号：KR1020000026472A

公开(公告)日：2000-05-15

申请号：KR1019980044003

申请日：1998-10-20

Applicant: 삼성전자주식회사

Inventor： 김기준

IPC: H03K3/00

Abstract: PURPOSE: An oscillation circuit is provided to change frequency according to peripheral condition, to externally regulate oscillation condition, and to eliminate a clock source. CONSTITUTION: An oscillation circuit includes a D flip-flop(10), many delay circuits(20, 50,60, 70), a multiplexer(40) and a selection-signal generation circuit(80). The D flip-flop(10) latches an input signal. The delay circuits(20, 50, 60, 70) delay the output signal from the D flip-flop(10). The multiplexer(40) selectively outputs one of the input signals from the delay circuits(20, 50, 60, 70), according to at least one selection signal. The selection-signal generation circuit(80) generates the selection signal corresponding to a signal applied from external.

Abstract translation: 目的：提供振荡电路，根据周边条件改变频率，外部调节振荡条件，消除时钟源。 构成：振荡电路包括D触发器（10），许多延迟电路（20,50,60,70），多路复用器（40）和选择信号产生电路（80）。 D触发器（10）锁存输入信号。 延迟电路（20,50,60,70）延迟来自D触发器（10）的输出信号。 多路复用器（40）根据至少一个选择信号选择性地输出来自延迟电路（20,50,60,70）的输入信号之一。 选择信号生成电路（80）生成与从外部施加的信号对应的选择信号。

公开(公告)号：KR100177747B1

公开(公告)日：1999-05-15

申请号：KR1019950037902

申请日：1995-10-28

Applicant: 삼성전자주식회사

Inventor： 김기준

IPC: G06F12/16

Abstract: 1. 청구범위에 기재된 발명이 속한 기술분야
이이피롬에 기록된 데이터를 보호하기 위한 회로.
2. 발명이 해결하려고 하는 기술의 과제
종래의 데이터 보호회로는 컨트롤 신호를 소프트웨어적인 방법으로 조정하거나, 난수발생회로를 사용함으로써 완벽한 보안성을 유지하기가 어려웠다.
3. 발명의 해결방법의 요지
이이피롬셀에 데이터의 저장과, 상기 저장된 데이터의 확인과정이 완료되면 전기적 합선을 이용한 물리적 방법으로 데이터입력단과 외부 출력단을 차단하는 회로.
4. 발명의 중요한 용도
이이피롬을 메모리로 사용하는 모든 회로.

公开(公告)号：KR1019980075801A

公开(公告)日：1998-11-16

申请号：KR1019970012122

申请日：1997-04-02

Applicant: 삼성전자주식회사

Inventor： 박경미 ,  김기준

IPC: H03K7/08

Abstract: 본 발명은 한 번의 데이터 입력만으로도 주파수를 변화시키지 않고 펄스폭을 확장할 수 있는 펄스폭 변조 회로에 관한 것으로서, 데이터 버스로부터 데이터를 입력받아 펄스폭을 변조하는 회로에 있어서, 소정비트신호를 카운팅하는 카운터와; 데이터 버스로부터 데이터를 인가받아 이를 저장하는 제 1 데이터 레지스터와; 카운터와 제 1 데이터 레지스터로부터 신호들을 인가받아 비교하는 제 1 비교기와; 상기 제 1 비교기로부터 매치신호를 인가받는 조합수단과; 데이터 버스로부터 데이터를 인가받아 이를 저장하는 제 2 데이터 레지스터와; 카운터와 제 2 데이터 레지스터로부터 신호들을 인가받아 이를 비교하는 제 2 비교기와; 상기 오버풀로우 신호, 조합부로부터 출력되는 신호, 상기 스트레치 신호를 인가받고, 상기 오버풀로우 신호가 뜰 때마다 펄스를 확장하여 출력하는 제어수단을 포함하는 펄스폭 변조회로.

公开(公告)号：KR1019930010130B1

公开(公告)日：1993-10-14

申请号：KR1019900018068

申请日：1990-11-09

Applicant: 삼성전자주식회사

Inventor： 김기준

IPC: H01L33/00

Abstract: The LED array has low contact registance on the electric poles and high light emission efficiency. The array includes a first conductive type junction layer formed on a substrate of first conductive type compound semiconductor, a second conductive diffusion layer formed on the junction layer to be separated for a light emitting part and an electrode contact part a 2nd conductive type electrode formed on the electrode contact part to be a separate electrode, and a 2st conductive type electrode formed on the bottom surface of the substrate to be a common electrode.

Abstract translation: LED阵列在电极上的接触记录低，发光效率高。 该阵列包括形成在第一导电类型化合物半导体的衬底上的第一导电类型结层，形成在用于发光部分分离的接合层上的第二导电扩散层和形成在第一导电类型化合物半导体上的第二导电型电极 所述电极接触部分为单独的电极，以及形成在所述基板的底表面上以形成公共电极的第二导电型电极。