Abstract:
A method for aligning nanostructures, such as nanowires, by using a self-assemblage process is provided to allow mass production of nanowires of which surface comprises an oxide, and to realize various surface nanostructures. A method for aligning nanowires of which surface comprises an oxide comprises the steps of: patterning a molecular membrane having the opposite charge to an oxide on the surface of a solid; dipping the patterned solid into a solution in which nanowires are dissolved; allowing the nanowires to be adsorbed onto a region where the molecular membrane is not patterned; and dissolving and removing the molecular membrane. The molecular membrane comprises at least one hydrophobic molecule selected from octadecytrichlorosilane(OTS), octadecyltrimethoxysilane(OTMS) and octadecytriethoxysilane(OTE).
Abstract:
본 발명은 나노구조를 탐침의 끝 부분에 선택적으로 흡착시키는 기술에 관한 것으로, 탐침 현미경의 탐침 끝 부분에 나노구조가 직접 선택적으로 흡착되거나, 링커분자를 거쳐 선택적으로 흡착되는 방법 및 그 탐침이 장착되어 해상도가 향상된 탐침 현미경에 관한 것이다. 탐침 현미경, 탐침, 나노입자, 나노구조, 선택적 흡착
Abstract:
본 발명은 나노구조를 탐침의 끝 부분에 선택적으로 흡착시키는 기술에 관한 것으로, 탐침 현미경의 탐침 끝 부분에 나노구조가 직접 선택적으로 흡착되거나, 링커분자를 거쳐 선택적으로 흡착되는 방법 및 그 탐침이 장착되어 해상도가 향상된 탐침 현미경에 관한 것이다. 탐침 현미경, 탐침, 나노입자, 나노구조, 선택적 흡착
Abstract:
PURPOSE: A device and a method for patterning with a dip-pen nanolithography method are provided to correct the defect of a photo-mask and broken circuit. CONSTITUTION: A probe(20) generates a capillary phenomenon by contacting with a substrate. An ink(40) covers the probe. A heat supply control unit(30) fluidifies the ink. The ink is transferred to the substrate by the capillary phenomenon. The heat supply control unit controls the temperature of the ink around the melting temperature of the ink.
Abstract:
A nonvolatile memory device and a method for forming the same are provided to improve an erasing speed of the nonvolatile memory device by including aluminum in only gate electrode among the gate electrode and a first blocking insulating layer. A tunnel insulating layer(110) is formed on a semiconductor substrate(100). A charge storage layer(120) is formed on the tunnel insulating layer. A first blocking insulation layer(140) is formed on the charge storage layer. A gate electrode(150) is formed on the first blocking insulation layer. The gate electrode includes aluminum among the gate electrode and the first blocking insulation layer.