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公开(公告)号：KR1020070112733A
公开(公告)日：2007-11-27
申请号：KR1020070049837
申请日：2007-05-22
Applicant: 재단법인서울대학교산학협력재단
Abstract: A method for aligning nanostructures, such as nanowires, by using a self-assemblage process is provided to allow mass production of nanowires of which surface comprises an oxide, and to realize various surface nanostructures. A method for aligning nanowires of which surface comprises an oxide comprises the steps of: patterning a molecular membrane having the opposite charge to an oxide on the surface of a solid; dipping the patterned solid into a solution in which nanowires are dissolved; allowing the nanowires to be adsorbed onto a region where the molecular membrane is not patterned; and dissolving and removing the molecular membrane. The molecular membrane comprises at least one hydrophobic molecule selected from octadecytrichlorosilane(OTS), octadecyltrimethoxysilane(OTMS) and octadecytriethoxysilane(OTE).
Abstract translation: 提供了通过使用自组装工艺来对准纳米线的纳米结构的方法，以允许批量生产表面包含氧化物的纳米线，并实现各种表面纳米结构。 用于对准其表面包含氧化物的纳米线的方法包括以下步骤：将具有相反电荷的分子膜图案化成固体表面上的氧化物; 将图案化固体浸入其中溶解纳米线的溶液中; 允许纳米线被吸附到分子膜未图案化的区域上; 并溶解和除去分子膜。 分子膜包含至少一种选自十八烷三氯硅烷（OTS），十八烷基三甲氧基硅烷（OTMS）和十八烷基三乙氧基硅烷（OTE）的疏水性分子。
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公开(公告)号：KR1020100016766A
公开(公告)日：2010-02-16
申请号：KR1020080076382
申请日：2008-08-05
Applicant: 재단법인서울대학교산학협력재단
CPC classification number: H05K1/032 , B82Y10/00 , H05K1/0393 , H05K1/167 , H05K3/207 , H05K2201/0162 , H05K2201/026 , H05K2201/0323 , H05K2203/0522 , H05K2203/105 , H05K2203/1173 , H05K2203/1453 , Y10T29/49117 , Y10T29/49121 , Y10T29/4913 , Y10T29/49155 , Y10T29/49162 , Y10T29/49165
Abstract: PURPOSE: A circuit board including a nanostructure and a manufacturing method thereof are provided to apply to a large area such as a wafer scale by forming a circuit aligned with a nanostructure on a polymer substrate. CONSTITUTION: A first electrode(112) and a second electrode(113) are located on the surface of a polymer substrate(111). A nanostructure(114) is electrically connected to a first electrode and a second electrode. The nanostructures is arranged to aligned along a lengthy direction of a pattern formed by at least one nanostructure.
Abstract translation: 目的：提供包括纳米结构的电路板及其制造方法，以通过在聚合物基板上形成与纳米结构对准的电路来应用于诸如晶片垢的大面积。 构成：第一电极（112）和第二电极（113）位于聚合物基板（111）的表面上。 纳米结构（114）电连接到第一电极和第二电极。 纳米结构被布置成沿着由至少一个纳米结构形成的图案的长度方向排列。
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公开(公告)号：KR101071325B1
公开(公告)日：2011-10-07
申请号：KR1020080076382
申请日：2008-08-05
Applicant: 재단법인서울대학교산학협력재단
CPC classification number: H05K1/032 , B82Y10/00 , H05K1/0393 , H05K1/167 , H05K3/207 , H05K2201/0162 , H05K2201/026 , H05K2201/0323 , H05K2203/0522 , H05K2203/105 , H05K2203/1173 , H05K2203/1453 , Y10T29/49117 , Y10T29/49121 , Y10T29/4913 , Y10T29/49155 , Y10T29/49162 , Y10T29/49165
Abstract: 회로기판제공방법은제1 기판을준비하는단계, 상기제1 기판상에회로-상기회로는제1 전극, 제2 전극및 적어도하나의나노구조물을구비함-를형성하는단계, 및상기회로를상기제1 기판으로부터중합체인제2 기판의표면으로전이시키는단계를구비한다.
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