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公开(公告)号：KR1020050032765A
公开(公告)日：2005-04-08
申请号：KR1020030068718
申请日：2003-10-02
Applicant: 한국전자통신연구원
IPC: H04L9/00
CPC classification number: H04L63/1416 , H04L63/0245
Abstract: A system for detecting/preventing in-line mode network intrusion and a method for the same are provided to rapidly respond to the network intrusion by processing the network intrusion and the invasion prevention in real time. A system for detecting/preventing in-line mode network intrusion includes a first network processor unit(221), a second network processor unit(231) and a personal computer(240). The first network processor unit(221) collects various statistical value data in response to the metering rule by monitoring the packet data unit(PDU) received from outside and selectively discards or passes the received PDU in response to the packet blocking rule and manufactures the copied PDU in response to the sensing rule. The second network processor unit(231) detects the protection and the intrusion state between the networks by using at least one invasion signature for the payload of the PDU received from the first network processor unit(221). And, the personal computer(240) generates or updates the packet prevention rule for preventing the intrusion detected from the second network processor unit(231) to supply the packet prevention rule to the first network processor unit(221).
Abstract translation: 提供用于检测/防止在线模式网络入侵的系统及其方法，以通过实时处理网络入侵和入侵防御来快速响应网络入侵。 用于检测/防止串联模式网络入侵的系统包括第一网络处理器单元（221），第二网络处理器单元（231）和个人计算机（240）。 第一网络处理器单元（221）通过监视从外部接收到的分组数据单元（PDU）来响应于计费规则来收集各种统计值数据，并且响应于分组阻塞规则选择性地丢弃或传递接收到的PDU，并且制造复制 PDU响应感测规则。 第二网络处理器单元（231）通过使用从第一网络处理器单元（221）接收的PDU的有效载荷的至少一个入侵签名来检测网络之间的保护和入侵状态。 并且，个人计算机（240）生成或更新用于防止从第二网络处理器单元（231）检测到的入侵的数据包防止规则，以将数据包防止规则提供给第一网络处理器单元（221）。
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公开(公告)号：KR1020010028927A
公开(公告)日：2001-04-06
申请号：KR1019990041459
申请日：1999-09-28
Applicant: 한국전자통신연구원
IPC: H04L12/28
CPC classification number: H04L12/5601 , H04L49/108 , H04L2012/5681 , H04L2012/5684
Abstract: PURPOSE: An ATM(Asynchronous Transfer Mode) switching system using a cell flow control device is provided to firstly control buffers of an input terminal, and to intercept a cell flow incoming to shared buffers of an output terminal. CONSTITUTION: Many input buffers(311-31N) receive cells inputted from many input lines, and temporally store the received cells. A nonblocking self rooting unit(320) receives the cells to root the cells as a switch output. A shared buffer(330) prevents a cell loss caused by an output blocking. Many output line interfaces(341-34N) interface the cells outputted from an exterior. A cell flow controller(350) receives input/output cells from the many input buffers(311-31N) and the shared buffer(330), and controls a cell flow control signal to the many input buffers(311-31N).
Abstract translation: 目的：提供使用信元流控制装置的ATM（异步传输模式）交换系统来首先控制输入终端的缓冲器，并拦截输入到输出终端的共享缓冲器的信元流。 构成：许多输入缓冲器（311-31N）接收从许多输入线输入的单元，并且临时存储所接收的单元。 非阻塞自生根单元（320）接收细胞以根据细胞作为开关输出。 共享缓冲器（330）防止由输出阻塞引起的信元丢失。 许多输出线接口（341-34N）接口从外部输出的单元。 单元流控制器（350）从许多输入缓冲器（311-31N）和共享缓冲器（330）接收输入/输出单元，并且控制到许多输入缓冲器（311-31N）的单元流控制信号。
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公开(公告)号：KR1019940007872B1
公开(公告)日：1994-08-26
申请号：KR1019910024028
申请日：1991-12-23
Abstract: The cyclic redundancy code (CRC) calculating circuit includes first and second 8-bit flip flops for retiming input and output data, an exclusive OR circuit for generating a next 8-bit register value for CRC calculation, an 8-bit register for latching data for CRC generation, a select circuit for inserting a CRC into a transfer data stream, and a delay circuit for supplying a control signal to the select circuit, thereby providing useful CRC calculation for high-speed data.
Abstract translation: 循环冗余码（CRC）计算电路包括用于重新定时输入和输出数据的第一和第二8位触发器，用于产生用于CRC计算的下一个8位寄存器值的异或电路，用于锁存数据的8位寄存器 用于CRC生成，用于将CRC插入到传输数据流中的选择电路，以及用于向选择电路提供控制信号的延迟电路，从而为高速数据提供有用的CRC计算。
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Patent Agency Ranking
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公开(公告)号：KR1019920005065B1
公开(公告)日：1992-06-26
申请号：KR1019890012183
申请日：1989-08-26
Abstract: A time switch communication path test command is received from a processor, and then, tests are performed on the normality of a testing and maintenance means (TTMA) and a control memory (TCMA). If they are normal, the operation proceeds, while if any one of them is abnormal, the abnormality is reported to a higher level. A testing line for the test of the comuncation path of the time switch unit is set in the control memory (TCMA), and the test pattern is transmitted through a testing line by controlling the testing and maintenance means (TTMA) and the control memory (TCMA). Then tests are carried out, and the test results are reported to a higher level.
Abstract translation: 从处理器接收时间切换通信路径测试命令，然后根据测试和维护手段（TTMA）和控制存储器（TCMA）的正常性执行测试。 如果正常，操作进行，如果其中任何一个异常，则报告异常。 在控制存储器（TCMA）中设置用于测试时间切换单元的连接路径的测试线，并且通过测试和维护手段（TTMA）和控制存储器（TTMA） TCMA）。 然后进行测试，测试结果报告更高。
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公开(公告)号：KR1019920005063B1
公开(公告)日：1992-06-26
申请号：KR1019890012181
申请日：1989-08-26
IPC: H04Q11/04
Abstract: The switch includes a plurality of second time switches (T0'- Tn'-1) which are so formed as to diplex each of first time switches (T-0Tn-1). A first diplexing means puts the first and second time switches in an active or standby position, and shifts them automatically when the status changes. Effective data bits are allocated on the first and second time switches and data links during the transmission of the between them, and the effective bits are monitored, thereby selecting a turned-on data from an appratus having the normal status. With the switch, the reliability of the apparatus is improved.
Abstract translation: 开关包括多个第二时间开关（T0'-Tn'-1），它们形成为使每个第一时间开关（T-0Tn-1）双工。 第一复用装置将第一和第二时间开关置于活动或待机位置，并且当状态改变时自动转换它们。 有效数据位在它们之间的传输期间在第一和第二时间交换机和数据链路上分配，并且有效位被监视，从而从具有正常状态的应用程序中选择接通的数据。 利用开关，改善了装置的可靠性。
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