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Patent Agency Ranking
公开(公告)号：KR1019940007555B1
公开(公告)日：1994-08-19
申请号：KR1019910022460
申请日：1991-12-07
IPC: H04Q11/04
Abstract: The method interfaces a master clock generation processor of a digital processing phase locked loop and a peripheral processor in low class processor board through a telephone device bus. The method includes the steps of: (A) checking that a peripheral processor (PP) is in normal mode when a data is transmitted from a master clock generation processor (MGCP); (B) reading a first byte of a transmission buffer and transmitting data when the first byte of a buffer is H'oo; (C) checking the first byte of a buffer after a certain number of tries when the first byte of a buffer is not H'oo; and (D) recording the abnormal state of a PP and terminating the transmission.
Abstract translation: 该方法通过电话设备总线将数字处理锁相环的主时钟生成处理器和低级处理器板中的外围处理器连接。 该方法包括以下步骤：（A）当从主时钟生成处理器（MGCP）发送数据时，（A）检查外围处理器（PP）处于正常模式; （B）当缓冲器的第一个字节为H'oo时读取发送缓冲区的第一个字节并发送数据; （C）当缓冲器的第一个字节不是H'oo时，在一定次数的尝试之后检查缓冲区的第一个字节; 和（D）记录PP的异常状态并终止传输。
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公开(公告)号：KR1019930002066B1
公开(公告)日：1993-03-22
申请号：KR1019890020673
申请日：1989-12-30
IPC: H04L7/00
Abstract: The circuit processes the data transmitted between networks without loss by supplying clock locked to both the clock of an oscillator and the reference clock. It includes a processor interfacing circuit (1) for processing oscillation control signal and data from a processor, a control signal generator (2) for generating buffer enable signal and latch enable signal, a latch circuit (4), a OVCXO (7) for controlling the frequency of the output clock, and a buffer circuit (3) for buffering the oscillator control signal and data.
Abstract translation: 电路通过提供锁定在振荡器的时钟和参考时钟的时钟来处理在网络之间传输的数据而不损失。 它包括用于处理来自处理器的振荡控制信号和数据的处理器接口电路（1），用于产生缓冲器使能信号和锁存使能信号的控制信号发生器（2），一个锁存电路（4），一个OVCXO（7） 控制输出时钟的频率，以及用于缓冲振荡器控制信号和数据的缓冲电路（3）。
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公开(公告)号：KR1019920005597B1
公开(公告)日：1992-07-09
申请号：KR1019890013187
申请日：1989-09-12
IPC: G06F1/00
Abstract: The circuit includes a manually operating means (3) for operating the circuit by manually manipulating switches. A preset signal generating means (5) generates pre-set signals at the instant when the manually operating means (3) is set, and a processor interface means (9) receives clock control data from a processor. A counter means (7) receives signals from the preset signal generating means and from the processor interface means to pre-set them by using the clock control data of the processor as the initial value. Upper and lower switches (1)(2) generate signals to increment or decrement the clock control data of the counter means, and a latching means (8) latches the clock control data of the counter means.
Abstract translation: 电路包括用于通过手动操作开关来操作电路的手动操作装置（3）。 预置信号发生装置（5）在手动操作装置（3）被设置的时刻产生预置信号，并且处理器接口装置（9）从处理器接收时钟控制数据。 计数器装置（7）从预设信号产生装置接收信号，并从处理器接口装置接收信号，以使用处理器的时钟控制数据作为初始值进行预设。 上下开关（1）（2）产生信号以递增或递减计数装置的时钟控制数据，锁存装置（8）锁存计数装置的时钟控制数据。
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