公开(公告)号：KR1020070057659A

公开(公告)日：2007-06-07

申请号：KR1020060115857

申请日：2006-11-22

Applicant: 한국전자통신연구원

Inventor： 최은아 ,  장대익 ,  오덕길

IPC: H03M13/11

CPC classification number: H03M13/1134 ,  H03M13/1165 ,  H03M13/6505 ,  H03M13/6522 ,  H03M13/6561

Abstract: An apparatus and a method for LDPC(Low Density Parity Check) decoding using a type-classified index are provided to optimize a memory structure and to manage a memory by using the type-classified index for controlling/managing the memory. An apparatus for LDPC decoding using a type-classified index includes an initialization/buffering block(100). The initialization/buffering block(100) multiplies received data by a channel estimation, and initially allocates the multiplied value to an LLR(Log Likelihood Ratio) memory block(110). The LLR memory block(110) consists of a plurality of memory blocks. A check node update block(120) updates a check node by using information stored in the LLR memory unit(110) and indexes stored in an index storage block(160). A bit node update block(130) updates a bit node by using the check node information updated in the check node update block(120). A decoding bit generation block(140) generates decoded data. An error symptom inspection block(150) determines whether a check node update and a bit node update are repeated or not by performing an error inspection for the decoded data. The index storage block(160) stores a ROM Index, an address Index, and a permutation index.

Abstract translation: 提供了使用类型分类索引的LDPC（低密度奇偶校验）解码的装置和方法，以通过使用用于控制/管理存储器的类型分类索引来优化存储器结构和管理存储器。 使用类型分类索引的LDPC解码装置包括初始化/缓冲块（100）。 初始化/缓冲块（100）通过信道估计对接收的数据进行乘法，并且首先将相乘的值分配给LLR（对数似然比）存储块（110）。 LLR存储块（110）由多个存储块组成。 校验节点更新块（120）通过使用存储在LLR存储器单元（110）中的信息和存储在索引存储块（160）中的索引来更新校验节点。 比特节点更新块（130）通过使用在校验节点更新块（120）中更新的校验节点信息来更新比特节点。 解码位产生块（140）产生解码数据。 错误症状检查块（150）通过对解码的数据执行错误检查来确定是否重复校验节点更新和比特节点更新。 索引存储块（160）存储ROM索引，地址索引和置换索引。

公开(公告)号：KR100454398B1

公开(公告)日：2004-10-26

申请号：KR1020010086515

申请日：2001-12-28

Applicant: 한국전자통신연구원

Inventor： 최은아 ,  장대익

IPC: H04L27/22

CPC classification number: H04L1/0054 ,  H03M13/256 ,  H03M13/41 ,  H04L1/0003 ,  H04L1/006 ,  H04L27/186

Abstract: Disclosed is a pragmatic decoder for receiving data encoded by an 8-PSK (phase shift keying) trellis encoder, and using a Viterbi decoder to decode the data, which comprises: an 8-PSK demodulator for demodulating signals transmitted by the trellis encoder; a quantizer for receiving signals from the 8-PSK demodulator, and using a constellation mapping configuration with reference to 0 degrees to detect n constellation position sections; and a soft decision unit for using a constellation position section detected by the quantizer to output a soft decision signal for converting it to I and Q signal arrangements needed for Viterbi decoder inputs.

Abstract translation: 公开了一种用于接收由8-PSK（相移键控）网格编码器编码的数据并且使用维特比解码器对数据进行解码的实用解码器，其包括：8-PSK解调器，用于解调由网格编码器发送的信号; 量化器，用于接收来自8-PSK解调器的信号，并使用参考0度的星座映射配置来检测n个星座位置部分; 以及软判定单元，用于使用量化器检测到的星座位置部分输出软判决信号，以将其转换为维特比解码器输入所需的I和Q信号配置。

公开(公告)号：KR100375823B1

公开(公告)日：2003-03-15

申请号：KR1020000083017

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 최은아 ,  김진호 ,  김내수 ,  오덕길

IPC: H03M13/41

CPC classification number: H03M13/6362 ,  H03M13/395 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107

Abstract: A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from ½code.

Abstract translation: 一种用于在设计维特比解码器的方法中通过使用基数-4分支度量计算器来设计维特比解码器时输入到维特比解码器的结构和方法，所述维特比解码器以高速解码穿孔码 ，被披露。 用于高速维特比解码器中基数-4分支度量计算的解套结构包括四个FIFO，四个多路复用器和一个基数-4分支度量计算器。 I和Q的两个输入比特流连接到两个较高的FIFO和两个较低的FIFO。 FIFO的输出端连接到下一级的上下多路复用器。 每个多路复用器的一个输出端连接到基数-4分支度量计算器。 结果，基数-4分支度量计算可以通过使用与输入I和Q比特流的时钟速度相同的时钟来实现。 该结构和该方法可以应用于从＆frac12; code派生的所有收缩代码的基数-4分支度量计算的收缩处理过程。