公开(公告)号：EP0907956B1

公开(公告)日：2000-05-31

申请号：EP97917123.8

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

公开(公告)号：EP1247299A1

公开(公告)日：2002-10-09

申请号：EP00959866.5

申请日：2000-08-31

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHANG, Chi ,  HUANG, Richard, J. ,  YOSHIE, Keizaburo ,  SUN, Yu

IPC: H01L27/105 ,  H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

公开(公告)号：EP1019914B1

公开(公告)日：2002-03-06

申请号：EP98919745.4

申请日：1998-04-10

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHEN, Pau-Ling ,  VAN BUSKIRK, Michael ,  HOLLMER, Shane, Charles ,  LE, Bing, Quang ,  KAWAMURA, Shoichi/ c/o Fujitsu Limited ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

公开(公告)号：EP1064679A1

公开(公告)日：2001-01-03

申请号：EP98963265.8

申请日：1998-12-17

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED ,  Fujitsu AMD Semiconductor Limited

Inventor： CHEN, Hung-Sheng ,  KIM, Unsoon ,  SUN, Yu ,  CHANG, Chi ,  RAMSBEY, Mark ,  RANDOLPH, Mark ,  KAJITA, Tatsuya ,  HUI, Angela ,  WANG, Fei ,  CHANG, Mark

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

公开(公告)号：EP0907956A1

公开(公告)日：1999-04-14

申请号：EP97917123.0

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.