公开(公告)号：WO1997049089A1

公开(公告)日：1997-12-24

申请号：PCT/US1997005218

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

Abstract translation: 本发明有助于编程所选择的浮动栅极器件，同时成功地禁止对未选择器件的编程，而不需要生长多个厚度的氧化物。 本发明的优选实施例利用多选择栅极器件。 特别地，选择栅极器件优选地是双浮置栅极器件，而不是在当前闪存存储器系统中用作选择栅极器件的常规晶体管（或用作常规晶体管的器件）。

公开(公告)号：EP0907956B1

公开(公告)日：2000-05-31

申请号：EP97917123.8

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

公开(公告)号：EP1019914A1

公开(公告)日：2000-07-19

申请号：EP98919745.4

申请日：1998-04-10

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHEN, Pau-Ling ,  VAN BUSKIRK, Michael ,  HOLLMER, Shane, Charles ,  LE, Bing, Quang ,  KAWAMURA, Shoichi ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

公开(公告)号：EP1019914B1

公开(公告)日：2002-03-06

申请号：EP98919745.4

申请日：1998-04-10

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHEN, Pau-Ling ,  VAN BUSKIRK, Michael ,  HOLLMER, Shane, Charles ,  LE, Bing, Quang ,  KAWAMURA, Shoichi/ c/o Fujitsu Limited ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

公开(公告)号：EP0907956A1

公开(公告)日：1999-04-14

申请号：EP97917123.0

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.