公开(公告)号：WO1991007816A1

公开(公告)日：1991-05-30

申请号：PCT/US1990006793

申请日：1990-11-20

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GILBERT, Barrie

IPC: H03F03/45

CPC classification number: H03F3/45479

Abstract: The apparatus includes an operational amplifier (56) which has inverting (72) and non-inverting (70) inputs and an output (74) that is a function of the voltage at the inverting and non-inverting inputs (72-70). An attenuator network (54) is connected to the operational amplifier (56). The attenuator network (54) includes circuitry for reducing a voltage of a first value at the inputs (62, 64) of the attenuator network (54) to a voltage that is a fraction of the first value at the output of the attenuator network (54) which voltage is then transmitted to the operational amplifier (56) inputs (70, 72). The attenuator network (54) includes additional circuitry (66) for reducing a common-mode feed-through voltage of a second value at the inputs (62, 64) ot the attenuator network (54) to a common-mode feed-through voltage that is a fraction of the second voltage at the output of the operational amplifier (56).

公开(公告)号：WO1991004609A1

公开(公告)日：1991-04-04

申请号：PCT/US1990005295

申请日：1990-09-18

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  LANE, Charles, D.

IPC: H03M01/36

CPC classification number: H03M1/206 ,  H03M1/361

Abstract: The invention comprises an n-bit analog-to-digital flash converter comprising 2n/2 input comparators, each having a first input coupled to receive the analog voltage to be converted and a second input coupled to a different reference voltage. The reference voltages of each consecutive input comparator are spaced apart two LSBs of the converter. Each input comparator has two outputs, OUT and an inverted version thereof, O^¨B7U^¨B7T^¨B7. 2n-1 consecutive latches are provided. Every other latch receives at its inputs the OUT and O^¨B7U^¨B7T^¨B7 signals from a single associated input comparator. All other latches receive the OUT signal of one of the input comparators and the O^¨B7U^¨B7T^¨B7 signal of an adjacent input comparator. The latches having inputs coupled to the OUT and O^¨B7U^¨B7T^¨B7 signals of a single input comparator produce a comparison output which change state every two LSBs of the converter and the latches having one input coupled to the OUT signal of one input comparator and the O^¨B7U^¨B7T^¨B7 signal of an adjacent input comparator produce comparison signals which change state halfway between the output signals of the adjacent latches. Thus, a comparison output is provided for every LSB of the full scale range of the converter using only 2n/2 input comparators.

公开(公告)号：WO1991003878A2

公开(公告)日：1991-03-21

申请号：PCT/US1990004885

申请日：1990-08-28

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: H03M01/06

CPC classification number: H03M1/0619 ,  H03M1/745 ,  H03M1/82

Abstract: A voltage coupling circuit for use in a digital-to-time converter insures that converter operation is stabilized against temperature and power supply variations. The digital-to-time converter operates by comparing a ramp voltage to a threshold voltage that is set in accordance with an input digital word. The voltage coupling circuit, which causes the ramp voltage to track changes in the threshold voltage, includes a current mirror arrangement that separates the voltage coupling and ramp generation functions. As a result, transistor base currents are not drawn through the ramp capacitor, and accuracy is improved in the case of long time delays.

公开(公告)号：WO1991002258A1

公开(公告)日：1991-02-21

申请号：PCT/US1990004296

申请日：1990-08-01

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MEANY, Richard, A. ,  SPEER, Raymond, J.

IPC: G01R31/28

CPC classification number: G06F11/006 ,  G01R31/31908

Abstract: In an integrated circuit package, a ROM is provided for identifying the device for testing purposes. The ROM is programmed, for example, by cutting resistor links. The resistor links set the output of the PROM. This output is a binary word which is read by the tester at the same time that the tester performs measurements on the reference device. With this information the tester can then perform various calculations.

公开(公告)号：WO1990006628A1

公开(公告)日：1990-06-14

申请号：PCT/US1989005389

申请日：1989-11-28

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  HILTON, E., Barry

IPC: H03K19/003

CPC classification number: G01R31/31924 ,  H03K19/00353 ,  H03K19/0826

Abstract: A technique and circuit for switching a bipolar output stage between an active mode in which the stage operates as a voltage source and an inhibit mode in which the stage is deactivated and the output node presents a floating high-impedance. The output stage may be in a digital device such as a digital pin driver circuit, or in an analog amplifier. Considering first the digital application, in the active mode, a digital output is switched between logic high and logic low voltages established by external references. The logic high and logic low reference voltages, and the corresponding output voltages, may be set to zero, a positive voltage or negative voltage independently of each other; a logic ''one'' can thus be set to a voltage below a logic ''zero''. When the output stage is an analog amplifier, in active mode it amplifies its input signal. In either arrangement, in the ''inhibit mode'', the output stage transistors are turned off by reverse-biasing their base-emitter junctions relative to the output node of the circuit, to provide a floating high-impedance output node. In the inhibit mode, additional means are provided for substantially cancelling leakage current at the output node.

Abstract translation: 一种技术和电路，用于在阶段作为电压源工作的有效模式和阶段被去激活的抑制模式和输出节点呈现浮动高阻抗之间切换双极性输出级。 输出级可以在诸如数字引脚驱动器电路的数字器件中，或在模拟放大器中。 首先考虑数字应用，在主动模式下，数字输出在逻辑高电平和由外部参考建立的逻辑低电压之间切换。 逻辑高和逻辑低参考电压以及相应的输出电压可以彼此独立地设置为零，正电压或负电压; 因此，逻辑“1”可被设置为低于逻辑“零”的电压。 当输出级是模拟放大器时，在有功模式下，放大其输入信号。 在任一种情况下，在“禁止模式”中，输出级晶体管通过相对于电路的输出节点反向偏置它们的基极 - 发射极结来截止，以提供浮动高阻抗输出节点。 在禁止模式中，提供了用于基本上消除输出节点处的泄漏电流的附加装置。

公开(公告)号：WO1990003066A1

公开(公告)日：1990-03-22

申请号：PCT/US1989003872

申请日：1989-09-07

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  TSUEI, Henry, T.

IPC: H03M01/36

CPC classification number: H03M1/164 ,  H03M1/0604 ,  H03M1/365 ,  H03M1/747

Abstract: A subranging converter employing a flash converter and a current-summing DAC which produces a current output. The DAC has a set of 2 - 1 current sources and 2 - 1 digital switches. Each switch channels its associated current source output either to the common output summing node or to ground. Each DAC switch, other than the first switch, takes its control input directly from an associated comparator in the flash converter. The direct connection between the comparators and the DAC eliminates the need for a video delay line and provides a fast conversion process.

Abstract translation: 采用闪存转换器的子转换器和产生电流输出的电流求和DAC。 DAC有一组2个n-1个电流源和2个n-1个数字开关。 每个开关将其相关联的电流源输出传送到公共输出求和节点或接地。 除了第一个开关之外，每个DAC开关直接从闪存转换器中的相关比较器控制输入。 比较器和DAC之间的直接连接消除了对视频延迟线的需要，并提供了快速的转换过程。

公开(公告)号：WO1988009035A2

公开(公告)日：1988-11-17

申请号：PCT/US1988000338

申请日：1988-02-05

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARDE, Douglas

IPC: G11C08/00

CPC classification number: G06F9/30141 ,  G11C8/16

Abstract: A multiport RAM register file adapted for flowing data directly from an input port to an output port and for simultaneously writing to a location in the register file. In addition to the RAM register, the apparatus includes (1) a first set of multiplexers between the input ports and the RAM, (2) a second set of multiplexers between the output of the RAM and the output ports and (3) logic for controlling the multiplexers and writing to the RAM. The input multiplexers are controlled by flow-through address comparators; the output multiplexers are controlled by read address comparators. The data at any input port of the register file may be written to any of the RAM data bit buses by selecting the input multiplexer appropriately. Because the bit buses are being driven, this data simultaneously may be passed to the RAM output just as if the RAM were being read, i.e., as a flow-through. Further, if the RAM address lines are activated concurrently, this data can be written to a selected cell while it is flowing-through to the output port. The output multiplexers feed the data from the bit lines to a selected output port (or ports).

公开(公告)号：WO1986007173A1

公开(公告)日：1986-12-04

申请号：PCT/US1986000250

申请日：1986-02-04

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ADAIR, Robert, L.

IPC: G06F07/50

CPC classification number: G06F7/501 ,  G06F2207/4812 ,  G06F2207/4816 ,  H03K19/0948 ,  H03K19/215

Abstract: A fast full adder cell, for use in multiplier arrays. The cell uses simple 2-input gates (16, 18, 22, 24) and a pair of multiplexers (11, 21) made from pass transistors (12, 14, 26, 28). The 2-input gates (16, 18, 22, 24) may also be made from pass transistors and, in the case of AND and OR gates, a single additional field-effect transistor. In a first embodiment, the cell employs a one-bit-wide multiplexer (11) for selecting as the sum output either the output of a 2-input exclusive-OR gate (16) or the output of a 2-input exclusive-NOR gate (18). A second one-bit-wide multiplexer (21) selects as the cell's carry output either the output of a 2-input OR gate (24) or the output of a 2-input AND gate (22). In a second embodiment, the 2-input exclusive-OR and exclusive-NOR gates also are formed from either one or two single-bit multiplexers (Figs. 3 and 4, respectively), while the AND and OR gates are formed from pass transistors (36, 42) with a pull-up or pull-down transistor (38, 44) on their outputs, as appropriates. Both the P-type device and the N-type device of each pass transistor are formed with the same minimum possible with; to compensate for unequal propagation of 1's and 0's, an inverter follows each pair of pass transistors and the P-type and N-type devices of the inverter are of approximately the same size.

Abstract translation: 一个快速全加器单元，用于乘法器阵列。 单元使用由传输晶体管（12,14,26,28）制成的简单的2输入栅极（16,18,22,24）和一对多路复用器（11,21）。 2输入栅极（16,18,22,24）也可以由传输晶体管制成，并且在AND和OR门的情况下，单个附加的场效应晶体管。 在第一实施例中，单元采用一位宽多路复用器（11），用于选择输出2-输入异或门（16）的输出或2-输入异或（NOR-NOR）的输出 门（18）。 第二个一比特多路复用器（21）选择2输入或门（24）的输出或2输入与门（22）的输出作为单元的进位输出。 在第二实施例中，2输入异或异或异或门也由一个或两个单比特多路复用器（分别为图3和4）形成，而AND和OR门由传输晶体管 （36,42），在其输出上具有上拉或下拉晶体管（38,44），作为适当的。 每个通过晶体管的P型器件和N型器件均以相同的最小值形成; 为了补偿1和0的不均匀传播，逆变器遵循每对传输晶体管，并且逆变器的P型和N型器件的尺寸大致相同。

公开(公告)号：WO1998028854A1

公开(公告)日：1998-07-02

申请号：PCT/US1997023561

申请日：1997-12-18

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURDEN, Franklin, M. ,  RAY, Harvey, J.

IPC: H03M01/44

CPC classification number: H03M1/44

Abstract: A high speed wide bandwidth peak detector (10) uses multiple peak detection stages (12a, 12b, ..., 12n) that detect different sub-ranges of a full-scale analog signal range. Splitting the peak detector into multiple stages reduces the number of taps in each stage, and hence their capacitance, which increases their bandwidth. The number of taps can be further reduced by using a non-uniform resolution of the desired full-scale amplitude range. In the preferred embodiment, identical peak detection stages are separated by fixed gain stages (14a, 14b, ..., 14n-1) that map the different sub-ranges to respective detection stages. This approach minimizes the effects of offset errors in the individual stages but requires gain stages that have wider bandwidths than the detection stages and which can be closely matched to maintain amplitude resolution.

Abstract translation: 高速宽带宽峰值检测器（10）使用检测满量程模拟信号范围的不同子范围的多个峰值检测级（12a，12b，...，12n）。 将峰值检测器分离成多个级别可以减少每个级中的抽头数量，从而减少其电容，从而增加其带宽。 可以通过使用期望的满量程幅度范围的不均匀分辨率来进一步减少抽头的数量。 在优选实施例中，相同的峰值检测级由固定增益级（14a，14b，...，14n-1）分开，其将不同子范围映射到相应的检测级。 这种方法最大限度地减少了各个阶段的偏移误差的影响，但是需要具有比检测级更宽带宽的增益级，并且可以紧密匹配以保持振幅分辨率。

公开(公告)号：WO1997045954A1

公开(公告)日：1997-12-04

申请号：PCT/US1997008981

申请日：1997-05-28

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MANGELSDORF, Christopher, W.

IPC: H03G01/00

CPC classification number: H03G7/06 ,  H03G1/0023

Abstract: A variable gain amplifier includes an input transconductor (10) having a transconductance that is variable in response to a first control signal (Ci), an output circuit (20) having a transresistance that is variable in response to the second control signal (Co) and a gain controller (30) responsive to a gain control signal x for providing the first and second control signals to the input transconductor and the output circuit. The amplifier has a voltage gain equal to the product of the transconductance and the transresistance. When the first control signal is a function (1 + x) of the gain control signal and the second control signal is a function (1 - x) of the gain control signal, the voltage gain of the amplifier is approximately an exponential function of the gain control signal.

Abstract translation: 可变增益放大器包括具有响应于第一控制信号（Ci）可变的跨导的输入跨导体（10），具有响应于第二控制信号（Co）可变的跨阻的输出电路（20） 以及响应于增益控制信号x的增益控制器（30），用于将第一和第二控制信号提供给输入跨导器和输出电路。 放大器的电压增益等于跨导和跨阻的乘积。 当第一控制信号是增益控制信号的函数（1 + x），而第二控制信号是增益控制信号的函数（1-x）时，放大器的电压增益近似为 增益控制信号。