Abstract:
An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.
Abstract:
The invention comprises an n-bit analog-to-digital flash converter comprising 2n/2 input comparators, each having a first input coupled to receive the analog voltage to be converted and a second input coupled to a different reference voltage. The reference voltages of each consecutive input comparator are spaced apart two LSBs of the converter. Each input comparator has two outputs, OUT and an inverted version thereof, O^¨B7U^¨B7T^¨B7. 2n-1 consecutive latches are provided. Every other latch receives at its inputs the OUT and O^¨B7U^¨B7T^¨B7 signals from a single associated input comparator. All other latches receive the OUT signal of one of the input comparators and the O^¨B7U^¨B7T^¨B7 signal of an adjacent input comparator. The latches having inputs coupled to the OUT and O^¨B7U^¨B7T^¨B7 signals of a single input comparator produce a comparison output which change state every two LSBs of the converter and the latches having one input coupled to the OUT signal of one input comparator and the O^¨B7U^¨B7T^¨B7 signal of an adjacent input comparator produce comparison signals which change state halfway between the output signals of the adjacent latches. Thus, a comparison output is provided for every LSB of the full scale range of the converter using only 2n/2 input comparators.
Abstract:
A protection circuit inhibits saturation and damage of sensitive circuit elements (54) when an input signal goes out of a nominal input range. The protection circuit includes an out-of-range detector (52) which compares the input signal to reference levels to determine if it is within the range. If it is not, a control circuit (62, 64) substitutes a supplemental signal that is slightly out of range, but not so far out of range as to cause any substantial saturation. Supplemental signal sources that produce supplemental signals slightly outside the high and low ends of the range with error margins, not more than about 750 mV, that lie just outside the range; an out-of-range input is replaced by the supplemental signal with the closest value. The invention is particularly applicable to multi-step/subranging analog-to-digital/converters.
Abstract:
Open-loop differential amplifiers (120, 140) are disclosed which have accurate and stable gain. The gain of these amplifiers is substantially insensitive to the effects of small-signal emitter resistance re, current gain beta and Early voltage VA. Thus, their gain can be accurately set by resistance ratios which makes them particularly useful in integrated circuits. These advantages are obtained with an output differential pair (67) that has cross-coupled base and collector terminals. In addition, resistors (141, 143, 148, 150) and a current source (146) associated with this differential pair are related to like elements (27, 28, 24, 25 and 26) that are associated with an input differential pair (21) by disclosed numerical ratios, e.g., the nominal gain G of the amplifier. Versions of the amplifiers can be adapted for use as a residue amplifier (162) in a subranging A/D converter (160).
Abstract:
A new differential ladder/comparator circuit reduces settling time delays in parallel analog-to-digital converters. A parallel analog-to-digital converter includes a pair of differential resistor ladders (L3, L4) having their taps connected to a group of comparators. The comparators produce digital "thermometer" scale outputs corresponding to analog signals impressed upon the differential ladders. By employing double-value resistors to form the "rungs" of the ladders and by connecting the comparators to the ladders taps in a way that increases the number of comparator inputs connected to the ladders' lower-order taps and decreases the number of comparator inputs connected to the ladders' higher order taps, the input impedance presented by the ladder/comparator combination is reduced in comparison with conventional differential ladder parallel ADCs. Additionally, input signal are superimposed on the ladders by drivers (Q1, Q2) which, in a preferred embodiment, present lower output impedances to the ladders than prior art drivers, further improving the bandwidth of the ADC.
Abstract:
An overvoltage protection circuit protects against saturation and damage of sensitive circuitry elements. The protection circuit includes an out-of-range detector (52) which compares an input signal to reference levels to determine if it is within a predetermined range of acceptable inputs. If the input is determined not to be within this range, a control circuit (62, 64) substitutes a supplemental signal within the range for the input signal. Digital correction can be provided to correct the output of the sensitive circuit element while the supplemental signal is being substituted. Numerous circuit designs may be used to implement the protection scheme.
Abstract:
An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.
Abstract:
An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.