公开(公告)号：US11093601B2

公开(公告)日：2021-08-17

申请号：US16664719

申请日：2019-10-25

Applicant: Apple Inc.

Inventor： Bernard J. Semeria ,  Devon S. Andrade ,  Jeremy C. Andrus ,  Ahmed Bougacha ,  Peter Cooper ,  Jacques Fortier ,  Louis G. Gerbarg ,  James H. Grosbach ,  Robert J. McCall ,  Daniel A. Steffen ,  Justin R. Unger

IPC: G06F21/44 ,  H04L9/32 ,  G06F15/78

Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.

公开(公告)号：US10901920B2

公开(公告)日：2021-01-26

申请号：US16380300

申请日：2019-04-10

Applicant: Apple Inc.

Inventor： Jainam A. Shah ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Kushal Dalmia ,  Pierre Habouzit ,  James M. Magee ,  Marina Sadini ,  Daniel A. Steffen

IPC: G06F9/46 ,  G06F12/14 ,  G06F9/48 ,  G06F9/52 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0842

Abstract: One embodiment provides for a computer-implemented method comprising instantiating a synchronization primitive to control access to a resource, acquiring the synchronization primitive at a first thread, the first thread having a first priority, associating a turnstile with the synchronization primitive, setting an inheritor of the turnstile to the first thread, attempting to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, the second thread having a second priority, adding the second thread to a wait queue of the turnstile; and in response to determining that the second priority is higher than the first priority, increasing the priority of the first thread to the second priority.

公开(公告)号：US10671430B2

公开(公告)日：2020-06-02

申请号：US15836411

申请日：2017-12-08

Applicant: Apple Inc.

Inventor： Daniel A. Steffen ,  Jainam A. Shah ,  James M. Magee ,  Jeremy C. Andrus ,  Russell A. Blaine

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54

Abstract: Techniques are disclosed relating to inter-process communication. In some embodiments, a kernel receives a notification of a communication to be sent from a first thread of a first application to a second thread of a second application. The kernel provides a reply port to the first thread for receiving a reply to the communication from the second thread. The kernel facilitates sending the communication from the first thread to the second thread. The kernel increases an execution priority of the second thread in response to the kernel determining that the reply port and a destination port associated with the second thread are identified in the communication. In some embodiments, the kernel creates the reply port in response to receiving the notification and, in response to detecting the reply has been communicated to the reply port, decreases the execution priority of the second thread and removes the reply port.

公开(公告)号：US20180349176A1

公开(公告)日：2018-12-06

申请号：US15870763

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

CPC classification number: G06F9/505 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/268 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4856 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/5044 ,  G06F9/5094 ,  G06F9/54 ,  G06F2209/501 ,  G06F2209/5018 ,  G06F2209/509

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US11422857B2

公开(公告)日：2022-08-23

申请号：US16882092

申请日：2020-05-22

Applicant: Apple Inc.

Inventor： Kushal Dalmia ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Nigel R. Gamble ,  James M. Magee ,  Daniel A. Steffen

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.

公开(公告)号：US10956220B2

公开(公告)日：2021-03-23

申请号：US15870760

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F1/3206 ,  G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US10891369B2

公开(公告)日：2021-01-12

申请号：US16664714

申请日：2019-10-25

Applicant: Apple Inc.

Inventor： Bernard J. Semeria ,  Devon S. Andrade ,  Jeremy C. Andrus ,  Ahmed Bougacha ,  Peter Cooper ,  Jacques Fortier ,  Louis G. Gerbarg ,  James H. Grosbach ,  Robert J. McCall ,  Daniel A. Steffen ,  Justin R. Unger

IPC: G06F21/44 ,  H04L9/32 ,  G06F15/78

Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.

公开(公告)号：US10884811B2

公开(公告)日：2021-01-05

申请号：US15870764

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US10417054B2

公开(公告)日：2019-09-17

申请号：US15870763

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/26 ,  G06F9/38 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30 ,  G06F1/3206

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20180349209A1

公开(公告)日：2018-12-06

申请号：US15836459

申请日：2017-12-08

Applicant: Apple Inc.

Inventor： Daniel A. Steffen ,  Pierre Habouzit ,  Daniel A. Chimene ,  Jeremy C. Andrus ,  James M. Magee ,  Puja Gupta

IPC: G06F9/52 ,  G06F9/48

Abstract: Techniques are disclosed relating to efficiently handling execution of multiple threads to perform various actions. In some embodiments, an application instantiates a queue and a synchronization primitive. The queue maintains a set of work items to be operated on by a thread pool maintained by a kernel. The synchronization primitive controls access to the queue by a plurality of threads including threads of the thread pool. In such an embodiment, a first thread of the application enqueues a work item in the queue and issues a system call to the kernel to request that the kernel dispatch a thread of the thread pool to operate on the first work item. In various embodiments, the dispatched thread is executable to acquire the synchronization primitive, dequeue the work item, and operate on it.