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    Systems and methods for reducing visual artifacts in displays due to refresh rate
    22.
    发明授权
    Systems and methods for reducing visual artifacts in displays due to refresh rate 有权

    公开(公告)号：US10964262B1

    公开(公告)日：2021-03-30

    申请号：US16414512

    申请日：2019-05-16

    Applicant: Apple Inc.

    Inventor： Chin-Wei Lin ,  Shinya Ono ,  Yun Wang

    IPC: G09G5/10 ,  G09G3/3233 ,  G09G3/20

    Abstract: Techniques for reducing image artifacts on a display s may include receiving image data, such that the image data includes pixel luminance data for a frame of image data. The technique may also include determining an emission duration for a pixel of the plurality of pixels during a sub-frame of the frame of image data based on the pixel luminance data. The technique may also include determining an emission duration extension to apply to the emission duration associated with the sub-frame based on a luminance baseline associated with the sub-frame, a luminance level associated with the sub-frame, and a time period associated with the sub-frame. The technique may then involve sending an emission signal to the pixel, such that the emission signal is configured to cause the pixel to emit light for a duration that correspond to the emission duration and the emission duration extension.

    Electronic display with hybrid in-pixel and external compensation
    24.
    发明授权
    Electronic display with hybrid in-pixel and external compensation 有权

    公开(公告)号：US11651736B2

    公开(公告)日：2023-05-16

    申请号：US17680059

    申请日：2022-02-24

    Applicant: Apple Inc.

    Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

    IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

    CPC classification number: G09G3/3258 ,  H01L27/3262 ,  H01L29/7869 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

    Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

    Display stack topologies for under-display optical transceivers
    25.
    发明授权
    Display stack topologies for under-display optical transceivers 有权

    公开(公告)号：US11592873B2

    公开(公告)日：2023-02-28

    申请号：US16791905

    申请日：2020-02-14

    Applicant: Apple Inc.

    Inventor： Xiao Xiang ,  Tong Chen ,  Fan Gui ,  Mark T. Winkler ,  Ran Tu ,  Tsu-Hui Lin ,  Wenrui Cai ,  Yun Wang

    IPC: G06F1/16 ,  G06F3/042 ,  G06F3/041

    Abstract: In some embodiments, a display stack includes a set of light-emitting elements, and a display backplane that includes a set of conductors and is electrically coupled to the set of light-emitting elements. A conductor in the set of conductors has a length, and a curved edge extending along at least a portion of the length. In some embodiments, a display stack includes a set of light-emitting elements; a set of transistors, electrically coupled to the set of light-emitting elements; and a set of conductors, electrically coupled to the set of transistors. The set of transistors may be electrically coupled to the set of conductors at a set of conductive pads. A plurality of conductive pads in the set of conductive pads is coupled to a single conductor in the set of conductors. The single conductor approaches different conductive pads in the plurality of conductive pads at different angles.

    Electronic display with hybrid in-pixel and external compensation
    27.
    发明授权
    Electronic display with hybrid in-pixel and external compensation 有权

    公开(公告)号：US10916198B2

    公开(公告)日：2021-02-09

    申请号：US16716911

    申请日：2019-12-17

    Applicant: Apple Inc.

    Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

    IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

    Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

    Electronic Display with Hybrid In-Pixel and External Compensation
    28.
    发明申请
    Electronic Display with Hybrid In-Pixel and External Compensation 有权

    公开(公告)号：US20210020109A1

    公开(公告)日：2021-01-21

    申请号：US17062786

    申请日：2020-10-05

    Applicant: Apple Inc.

    Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

    IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

    Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

    Brightness control architecture
    30.
    发明授权
    Brightness control architecture 有权

    公开(公告)号：US10304411B2

    公开(公告)日：2019-05-28

    申请号：US15347611

    申请日：2016-11-09

    Applicant: Apple Inc.

    Inventor： Koorosh Aflatooni ,  Sang Y. Youn ,  Mohammad Hajirostam ,  Yun Wang

    IPC: G09G3/32 ,  G09G5/10

    Abstract: Display panels and methods for operating a display panel are described. In an embodiment, the display panel includes a plurality of pixels arranged in rows and columns, a plurality of rows of emission control lines extending through the plurality of rows of pixels, and a global emission line coupled to the plurality of rows of emission control lines. Modes of operation of the display panel include global flash mode and low persistence mode.

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