公开(公告)号：US07282124B2

公开(公告)日：2007-10-16

申请号：US10459320

申请日：2003-06-10

Applicant: Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

Inventor： Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

IPC: C25D17/00

CPC classification number: B23H3/04 ,  B23H5/08 ,  C25D5/08 ,  C25D17/00 ,  C25D17/001 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.

公开(公告)号：US20060011485A1

公开(公告)日：2006-01-19

申请号：US11232026

申请日：2005-09-20

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D5/10 ,  C25D5/02

CPC classification number: C25D5/02 ,  C25D5/22 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76877

Abstract: The present invention relates to a method for forming a planar conductive surface on a wafer. In one aspect, the present invention uses a no-contact process with electrochemical deposition, followed by a contact process with electrochemical mechanical deposition.

公开(公告)号：US06942780B2

公开(公告)日：2005-09-13

申请号：US10460032

申请日：2003-06-11

Applicant: Bulent M. Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent M. Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D7/12 ,  C25D17/00 ,  C25D17/08 ,  C25D21/00 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  C25D5/00 ,  C25D5/08 ,  C25F3/00

CPC classification number: C25D5/02 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76877

Abstract: An apparatus for processing a material on a wafer surface includes a cavity defined by a peripheral wall and configured to direct a process solution and direct it to the surface to to a first wafer surface region without being directed to a second wafer surface region, a head configured to hold the wafer so that the surface of the wafer faces the cavity, and an electrical contact member positioned outside the cavity peripheral wall and configured to contact the second wafer surface region extending beyond the cavity, when the wafer is moved relative to the contact member. Advantages of the invention include substantially full surface treatment of the wafer.

Abstract translation: 用于处理晶片表面上的材料的设备包括由周壁限定的空腔，并且被配置为引导处理溶液并将其引导到表面到达第一晶片表面区域而不被引导到第二晶片表面区域，头部 被配置为保持所述晶片使得所述晶片的表面面向所述空腔;以及电接触构件，其定位在所述腔周壁外部并且被配置为当所述晶片相对于所述触点移动时接触延伸超过所述腔的所述第二晶片表面区域 会员。 本发明的优点包括晶片的基本全表面处理。

公开(公告)号：US20050145489A1

公开(公告)日：2005-07-07

申请号：US11054053

申请日：2005-02-08

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Halit Yakupoglu ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Halit Yakupoglu ,  Homayoun Talieh

IPC: B23H5/08 ,  C25F3/14 ,  H01L21/288 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  C25B9/00 ,  C25D17/00

CPC classification number: H01L21/32115 ,  B23H5/08 ,  C25F3/14 ,  H01L21/2885 ,  H01L21/32134 ,  H01L21/7684

Abstract: A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.

公开(公告)号：US20050133380A1

公开(公告)日：2005-06-23

申请号：US10996165

申请日：2004-11-22

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Paul Lindquist ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Paul Lindquist ,  Homayoun Talieh

IPC: B23H5/08 ,  C25D5/22 ,  C25D7/12 ,  C25F3/14 ,  C25F7/00 ,  H01L21/3213 ,  B23H3/00

CPC classification number: C25D17/001 ,  B23H5/08 ,  C25D5/22 ,  C25F3/14 ,  C25F7/00 ,  H01L21/32134

Abstract: The present invention applies an electrochemical etching solution to a material layer, preferably a metal layer, disposed on a workpiece, in the presence of a current. This electrochemical etching solution supplies to the material on the substrate surface the species to form an intermediate compound on the surface that can be more easily mechanically removed as intermediate compound fragments than the material. By removing the intermediate compound fragments, the process allows more efficient use of the supplied current to form another layer of intermediate compound that can also be mechanically removed, rather than using the current to result in another compound on the surface of the material that eventually dissolves into the solution. In another aspect of the invention, such intermediate compound particulates are externally generated and used to mechanically remove the surface layer of the material. Such intermediate particulates do not contaminate, and thus allow for more efficient material removal, as well as plating to occur within the same chamber, if desired.

Abstract translation: 本发明在存在电流的情况下将电化学蚀刻溶液应用于设置在工件上的材料层，优选金属层。 该电化学蚀刻溶液向基材表面上的材料提供物质，以在表面上形成中间体化合物，其可以比材料作为中间体化合物片段更容易地机械去除。 通过去除中间体化合物片段，该方法允许更有效地使用所提供的电流以形成也可机械去除的另一层中间体化合物，而不是使用电流在材料表面上产生最终溶解的另一种化合物 进入解决方案。 在本发明的另一方面，这种中间体化合物颗粒是外部生成的并用于机械地去除材料的表面层。 如果需要，这样的中间颗粒不会污染，因此允许更有效的材料去除以及电镀发生在相同的室内。

公开(公告)号：US06478936B1

公开(公告)日：2002-11-12

申请号：US09568584

申请日：2000-05-11

Applicant: Rimma Volodarsky ,  Konstantin Volodarsky ,  Cyprian Uzoh ,  Homayoun Talieh ,  Douglas W. Young

Inventor： Rimma Volodarsky ,  Konstantin Volodarsky ,  Cyprian Uzoh ,  Homayoun Talieh ,  Douglas W. Young

IPC: C25B1103

CPC classification number: C25D17/14 ,  C25F7/00

Abstract: A particular anode assembly can be used to supply a solution for any of a plating operation, a planarization operation, and a plating and planarization operation to be performed on a semiconductor wafer. The anode assembly includes a rotatable shaft disposed within a chamber in which the operation is performed, an anode housing connected to the shaft, and a porous pad support plate attached to the anode housing. The support plate has a top surface adapted to support a pad which is to face the wafer, and, together with the anode housing, defines an anode cavity. A consumable anode may be provided in the anode cavity to provide plating material to the solution. A solution delivery structure by which the solution can be delivered to said anode cavity is also provided. The solution delivery structure may be contained within the chamber in which the operation is performed. A shield can also be mounted between the shaft and an associated spindle to prevent leakage of the solution from the chamber.

Abstract translation: 可以使用特定的阳极组件来提供用于在半导体晶片上进行的电镀操作，平面化操作和电镀和平面化操作中的任何一种的解决方案。 阳极组件包括设置在其中执行操作的室内的可旋转轴，连接到轴的阳极壳体和附接到阳极壳体的多孔垫支撑板。 支撑板具有适于支撑面向晶片的焊盘的顶表面，并且与阳极壳体一起限定阳极腔。 可以在阳极腔中设置消耗性阳极以向溶液提供电镀材料。 还提供了可以将溶液输送到所述阳极腔的溶液输送结构。 溶液输送结构可以包含在进行操作的室内。 护罩还可以安装在轴和相关主轴之间，以防止溶液从腔室泄漏。

公开(公告)号：US06354916B1

公开(公告)日：2002-03-12

申请号：US09544558

申请日：2000-04-06

Applicant: Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

Inventor： Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

IPC: B24B100

CPC classification number: B24B37/042 ,  C25D3/38 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A modified plating solution that can be used to electroplate a high quality conductive material that can be effectively polished and planarized includes (1) a solvent, (2) an ionic species of the conductive material to be deposited, (3) at least one additive to improve electrical and structural properties, and (4) a modifying agent.

公开(公告)号：US08816505B2

公开(公告)日：2014-08-26

申请号：US13193814

申请日：2011-07-29

Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

IPC: H01L23/48 ,  H01L21/283

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Abstract translation: 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

公开(公告)号：US08742541B2

公开(公告)日：2014-06-03

申请号：US13182890

申请日：2011-07-14

Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia ,  Vage Oganesian

Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia ,  Vage Oganesian

IPC: H01L21/02 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L23/642 ,  H01G4/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/16 ,  H01L28/40 ,  H01L28/91 ,  H01L28/92 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape.

Abstract translation: 电容器可以包括具有第一表面的基板，远离第一表面的第二表面，以及在第一和第二表面之间延伸的通孔，第一和第二金属元件以及将第一和第二表面分离和绝缘的电容器介电层 至少在通孔内的金属元​​件彼此之间。 第一金属元件可以在第一表面暴露并且可以延伸到通孔中。 第二金属元件可以在第二表面处露出并且可以延伸到通孔中。 第一和第二金属元件可以电连接到第一和第二电位。 电容器介电层可以具有起伏的形状。

公开(公告)号：US08728934B2

公开(公告)日：2014-05-20

申请号：US13168839

申请日：2011-06-24

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。 另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。