公开(公告)号：JP2004335921A

公开(公告)日：2004-11-25

申请号：JP2003132748

申请日：2003-05-12

Applicant: Fujikura Ltd ,  株式会社フジクラ

Inventor： OKAMOTO MASAHIRO

IPC: H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To increase the packing density of an electronic component or the like both by increasing the fixing strength of a copper land and by reducing connection resistance. SOLUTION: The opening diameter Da of a via hole 14 in an insulating base material 14A is different from the opening diameter Db of an adhesive layer 14B in two steps. The opening diameter Da of the insulating base material 14A is smaller than the opening diameter Db of the adhesive layer 14B. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004235555A

公开(公告)日：2004-08-19

申请号：JP2003024437

申请日：2003-01-31

Applicant: Fujikura Ltd ,  株式会社フジクラ

Inventor： HONTO KOJI ,  NAKAO SATORU ,  NAGATA MASAKATSU ,  OKAMOTO MASAHIRO

IPC: H05K3/46

Abstract: PROBLEM TO BE SOLVED: To obtain a multilayer circuit board, where electric resistance in a multilayer connection electric circuit is low and electric characteristics are excellent.
SOLUTION: A conductive paste 16 filled into a through hole 14 is sucked from the side of a bonding layer 13 by negative pressure air in a non-contact state for forming a projection 15B that projects outside from a surface at the side of the bonding layer 13 and has a rotation curve shape.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004134467A

公开(公告)日：2004-04-30

申请号：JP2002295404

申请日：2002-10-08

Applicant: Fujikura Ltd ,  株式会社フジクラ

Inventor： NAKAO SATORU ,  NAGATA MASAKATSU ,  WATANABE TARO ,  OKAMOTO MASAHIRO ,  ITO SHOJI

IPC: H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To obtain a multilayered wiring board that shows high ion migration resistance, contains a multilayered connecting electric circuit having low electrical resistance, and is excellent in electrical characteristic. SOLUTION: A conductive section composed of a conductive resin packed in a via hole 14 is constituted in a double structure of a first conductive section 15 composed of a conductive resin covering the inner peripheral surface of the hole 14 and containing a conductive filler other than silver, and a second conductive section 16 composed of a conductive resin filling up the inside of the first conductive section 15 and containing a conductive filler composed mainly of silver. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004095963A

公开(公告)日：2004-03-25

申请号：JP2002257041

申请日：2002-09-02

Applicant: Fujikura Ltd ,  株式会社フジクラ

Inventor： ITO SHOJI ,  OKAMOTO MASAHIRO ,  NAKAO SATORU

IPC: H05K3/46

Abstract: PROBLEM TO BE SOLVED: To stably ensure enough interlayer bonding strength without having an influence on the bonding strength after multilayer lamination even when a bonding layer by heating and sticking is formed on a copper-clad resin backing and the like.
SOLUTION: For a thermoplastic polyimide sheet 13 having a thermosetting function there is used one where a glass transition point Tg of thermoplastic polyimide is lower than the curing start temperature Ts of a thermosetting component. A process for sticking the thermoplastic polyimide sheet 13 having a thermosetting function to the copper-clad resin backing is performed at a higher temperature than the glass transition temperature Ts of the thermoplastic polyimide and at a lower temperature than the curing starting temperature Ts of the thermosetting starting temperature Ts of the thermosetting component. In a multilayering process, the thermoplastic polyimide sheet 13 having a thermosetting function is stuck at a higher temperature than the curing starting temperature Ts of the thermosetting component.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004039056A

公开(公告)日：2004-02-05

申请号：JP2002192542

申请日：2002-07-01

Applicant: Fujikura Ltd ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社フジクラ

Inventor： NASU YOSHIO ,  NAKAO SATORU ,  NAGATA MASAKATSU ,  OKAMOTO MASAHIRO ,  IWASAKI SHOJI ,  MIZUTANI MUNEKIMI ,  ITO SHOJI ,  PONPANPAANII ANAN ,  ISHIKAWA HIROMI ,  UEMATSU YOSHIO ,  SHI ARASHI ,  YOSHIDA TATSUSHI

IPC: G11B5/60 ,  G11B21/21 ,  H05K1/02 ,  H05K3/00 ,  H05K3/28

Abstract: PROBLEM TO BE SOLVED: To prevent peeling or separation of a polyimide insulating material caused by the pie-doughy irregularities during the wet etching of the polyimide insulating material in a circuit integrated suspension and a flexible circuit board.
SOLUTION: The vicinity of a pie-doughy irregular part formed when a polyimide insulating material is patterned by wet etching is covered with thermosetting resin, photosetting resin or a precursor thereof.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003318546A

公开(公告)日：2003-11-07

申请号：JP2003029816

申请日：2003-02-06

Applicant: Fujikura Ltd ,  株式会社フジクラ

Inventor： ITO SHOJI ,  HIGUCHI REIJI ,  OKAMOTO MASAHIRO ,  NAKAO SATORU

IPC: H05K1/11 ,  H01L23/12 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a base material for a multilayer wiring board by which a thin multilayer wiring board can be obtained without failing connection reliability between a conductive resin composition and a conductive circuit and lowering the flatness of the board. SOLUTION: The diameter of a conductive layer 14b of a through hole 14 is made smaller than those of an insulation layer and an adhesion layer part 14a, and conductive connection between a conductive resin composition 15 and a conductive layer 12 is ensured on the rear surface 12a of the conductive layer 12, and then the conductive layer 14b is also filled with the conductive resin composition 15 in addition to the insulation layer and the adhesion layer part 14a. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：为了提供可以获得薄多层布线板的多层布线板的基材，而不会导致导电树脂组合物和导电电路之间的连接可靠性降低，并且降低板的平坦度。 解决方案：使通孔14的导电层14b的直径小于绝缘层和粘合层部分14a的直径，并且确保导电树脂组合物15与导电层12之间的导电连接 除了绝缘层和粘合层部分14a之外，导电层12的后表面12a，然后导电层14b也填充有导电树脂组合物15。 版权所有（C）2004，JPO

公开(公告)号：JP2003162804A

公开(公告)日：2003-06-06

申请号：JP2001361374

申请日：2001-11-27

Applicant: FUJIKURA LTD

Inventor： NAGATA MASAKATSU ,  NAKAO SATORU ,  IWASAKI SHOJI ,  MIZUTANI MUNEKIMI ,  NASU YOSHIO ,  OKAMOTO MASAHIRO ,  HIGUCHI REIJI ,  ITO SHOJI

IPC: G11B5/60 ,  G11B21/21

Abstract: PROBLEM TO BE SOLVED: To provide a suspension for a magnetic head capable of improving the structure of a circuit conductor fixed to the suspension for the magnetic head, increasing the amount of a writing signal current, and dealing with a high-speed transmission. SOLUTION: The suspension with a circuit for the magnetic head includes a sheet-like insulating layer 20 and a plurality of circuits consisting of the conductor and corresponding to a plurality of signals, respectively, and is constituted by disposing these circuits on a surface 20a of the insulating layer. Each of the circuits is divided into two or more along the direction of a longitudinal axis line, and the insulators 31c and 32c intervene between the divided circuit 31a, 32a and the circuit 31b, 32b, respectively. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2010199224A

公开(公告)日：2010-09-09

申请号：JP2009041032

申请日：2009-02-24

Applicant: Fujikura Ltd ,  株式会社フジクラ

Inventor： OKAMOTO MASAHIRO

IPC: H01L23/12 ,  H01L21/60

CPC classification number: H01L24/81 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/14135 ,  H01L2224/16 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16238 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package which has an IC chip mounted upright on a substrate and held in an upright mounted state without being laterally drawn by the surface tension of solder, and can be easily made short in height.
SOLUTION: The semiconductor package 1A(1) includes at least an insulating substrate 11, a printed wiring board 10 arranged on one surface thereof and composed of wiring 12, and the IC chip 20 mounted to one surface side of the insulating substrate and having an integrated circuit 22 and re-wiring 24 on a principal surface. The insulating substrate has a cavity 13 which is opened on its one surface, the IC chip is put at least partially in the cavity and has the principal surface where the integrated circuit is disposed along an inner surface of the cavity, and the re-wiring of the IC chip and the wiring of the printed wiring board are electrically connected to each other through solder 14.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体封装，其具有直立安装在基板上并保持在直立安装状态的IC芯片，而不会被焊料的表面张力横向拉伸，并且可以容易地使其高度短。 解决方案：半导体封装1A（1）至少包括绝缘基板11，布置在其一个表面上并由布线12组成的印刷布线板10和安装在绝缘基板的一个表面侧的IC芯片20 并且在主表面上具有集成电路22和重新布线24。 绝缘基板具有在其一个表面上开口的空腔13，IC芯片至少部分地放置在空腔中，并且具有集成电路沿着空腔的内表面设置的主表面，并且重新布线 的IC芯片和印刷电路板的布线通过焊料14彼此电连接。版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010098064A

公开(公告)日：2010-04-30

申请号：JP2008266590

申请日：2008-10-15

Applicant: Fujikura Ltd ,  株式会社フジクラ

Inventor： OKAMOTO MASAHIRO

IPC: H01L23/12

CPC classification number: H01L2224/18

Abstract: PROBLEM TO BE SOLVED: To provide a laminated wiring board which incorporates a thinned semiconductor element of low contact resistance and is suitable for obtaining an easy-to-assemble and thinned package structure, and a method for manufacturing the same. SOLUTION: In the laminated wiring board for which the semiconductor element is incorporated, attached and sealed between a first substrate material and a second substrate material disposed facing each other, the first substrate material includes a wiring board with a wiring layer formed on one surface of an insulating substrate, and a through electrode made of conductive paste, which passes through the insulating substrate and whose one end face is connected to the wiring layer and other end face is exposed to the other surface of the insulating substrate. The semiconductor element includes an electrode pad formed on the partial surface of the semiconductor substrate, an inorganic insulating film on the surface of the semiconductor substrate with a contact hole to the electrode pad, a re-wiring layer on it, an organic insulating film provided with the contact hole for it and formed on the surface of the re-wiring layer, and a protective conductive layer for covering the surface of the re-wiring layer inside the contact hole. The other end face of the through electrode is connected through the protective conductive layer to the re-wiring layer. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种结合了具有低接触电阻的薄化半导体元件并且适于获得易于组装和变薄的封装结构的层压布线板及其制造方法。 解决方案：在将半导体元件并入的层叠配线基板中，第一基板材料和第二基板材料彼此相对配置的第一基板材料附着并密封，第一基板材料包括布线板，其布线层形成在 绝缘基板的一个表面和通过绝缘基板并且其一个端面连接到布线层和另一个端面的由导电浆料制成的通孔暴露于绝缘基板的另一个表面。 半导体元件包括形成在半导体衬底的部分表面上的电极焊盘，在半导体衬底的表面上具有与电极焊盘的接触孔的无机绝缘膜，其上的再布线层，设置有机绝缘膜 并且形成在再布线层的表面上的接触孔，以及用于覆盖接触孔内的再布线层的表面的保护导电层。 通孔电极的另一个端面通过保护导电层连接到再布线层。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008270362A

公开(公告)日：2008-11-06

申请号：JP2007108520

申请日：2007-04-17

Applicant: Fujikura Ltd ,  株式会社フジクラ

Inventor： OKAMOTO MASAHIRO

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H01L2224/16225 ,  H01L2924/15311

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer wiring board which has a thinned semiconductor element maintaining planarity and is suitable to obtain an easily assembled thinned package structure, and to provide a manufacturing method thereof. SOLUTION: The multilayer wiring board has a structure in which a semiconductor element 3 is bonded between first and second substrate materials 1 and 2 which are face-to-face disposed. In the wiring board, the first substrate material 1 is provided with a wiring board having a wiring layer 1b formed on one surface of an insulating substrate 1a, and a through electrode 1c made of a conductive paste, piercing through the insulating substrate, having one end surface connected to the wiring layer and the other end surface exposed on the other surface of the insulating substrate. The semiconductor substrate 3 is provided with an electrode pad 3b formed on one surface of the semiconductor substrate 3a, an inorganic insulating film 3c having a contact hole for the electrode pad and formed on the surface of the semiconductor substrate, and a re-wiring layer 3d formed on the inorganic insulating film and connected to the electrode pad, and the other end surface of the through electrode 1c is connected to the re-wiring layer 3d. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有保持平坦度的薄化半导体元件并且适于获得易于组装的薄化封装结构的多层布线板，并提供其制造方法。 解决方案：多层布线板具有半导体元件3接合在面对面布置的第一和第二基板材料1和2之间的结构。 在布线基板中，第一基板材料1设置有布线基板，该布线基板具有形成在绝缘基板1a的一个表面上的布线层1b，以及由导电浆料制成的贯通绝缘基板的贯通电极1c， 所述端面与所述布线层连接，所述另一端表面暴露在所述绝缘基板的另一表面上。 半导体基板3设置有形成在半导体基板3a的一个表面上的电极焊盘3b，具有用于电极焊盘的接触孔并形成在半导体基板的表面上的无机绝缘膜3c和再布线层 3d形成在无机绝缘膜上并连接到电极焊盘，并且贯通电极1c的另一个端面连接到再布线层3d。 版权所有（C）2009，JPO＆INPIT