公开(公告)号：US12281996B2

公开(公告)日：2025-04-22

申请号：US17808176

申请日：2022-06-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Ramsey M. Hazbun ,  John J. Ellis-Monaghan

IPC: G01N27/06 ,  H10F30/223 ,  H10F71/00 ,  H10F77/14

Abstract: Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

公开(公告)号：US12040252B2

公开(公告)日：2024-07-16

申请号：US17858660

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Cameron Luce ,  Siva P. Adusumilli ,  Mark Levy

IPC: H01L23/473 ,  H01L21/762 ,  H01L23/367 ,  H01L29/51

CPC classification number: H01L23/473 ,  H01L21/76229 ,  H01L23/367 ,  H01L29/515

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

公开(公告)号：US20240222366A1

公开(公告)日：2024-07-04

申请号：US18604627

申请日：2024-03-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L21/8258 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0605 ,  H01L21/8258 ,  H01L27/0623 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

公开(公告)号：US12028053B2

公开(公告)日：2024-07-02

申请号：US17643567

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H03K17/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/12 ,  H03K17/693

CPC classification number: H03K17/102 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/1203 ,  H03K17/693 ,  H03K2217/0018

Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

公开(公告)号：US20240159962A1

公开(公告)日：2024-05-16

申请号：US17985223

申请日：2022-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark Levy ,  Siva P. Adusumilli ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B2006/12078

Abstract: Structures for a waveguide and methods of forming a waveguide. The structure comprises a substrate, a waveguide core comprising a compound semiconductor material, and a layer disposed on the substrate. The layer comprises the compound semiconductor material, and the layer includes a cavity positioned beneath the waveguide core.

公开(公告)号：US11972999B2

公开(公告)日：2024-04-30

申请号：US17643023

申请日：2021-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Rajendran Krishnasamy ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H01L23/367 ,  H01L23/373 ,  H01L29/417 ,  H01L29/732

CPC classification number: H01L23/367 ,  H01L23/3736 ,  H01L29/41708 ,  H01L29/7325

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

公开(公告)号：US20240068985A1

公开(公告)日：2024-02-29

申请号：US17821836

申请日：2022-08-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Laura J. Silverstein

IPC: G01N27/414 ,  B01L3/00 ,  G01N21/05

CPC classification number: G01N27/4145 ,  B01L3/502715 ,  G01N21/05 ,  B01L2300/047 ,  B01L2300/0636 ,  B01L2300/0645

Abstract: A structure includes a lab-on-chip (LOC) sensor and frontside port and cavity features for conveying a flowable sample (fluid or gas) to a sensing element of the sensor. The cavity is confined within middle of the line (MOL) dielectric layer(s). Alternatively, the cavity includes a lower section within MOL dielectric layer(s), an upper section within back end of the line (BEOL) dielectric layer(s) in the first metal (M1) level, a divider between the sections, and a duct linking the sections. Alternatively, the cavity includes a lower portion within MOL dielectric layer(s) and an upper portion continuous with the lower portion and within BEOL dielectric layer(s) in the M1 level. Optionally, the cavity is separated from the sensing element by an additional dielectric layer and/or at least partially lined with a dielectric liner. The port extends from the top of the BEOL dielectric layers down to the cavity.

公开(公告)号：US11901304B2

公开(公告)日：2024-02-13

申请号：US17323423

申请日：2021-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sunil K. Singh ,  Vibhor Jain ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  Johnatan A. Kantarovsky ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L23/481 ,  H01L23/57 ,  H01L23/573 ,  H01L2223/5442 ,  H01L2223/54433

Abstract: The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

公开(公告)号：US11862511B2

公开(公告)日：2024-01-02

申请号：US17527716

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Alvin Joseph

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76297 ,  H01L21/02595

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.

公开(公告)号：US20230405582A1

公开(公告)日：2023-12-21

申请号：US17807896

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Ramsey M. Hazbun ,  Siva P. Adusumilli ,  Mark D. Levy

IPC: B01L3/00 ,  G01N27/414

CPC classification number: B01L3/502715 ,  B01L2200/12 ,  G01N27/414 ,  B01L3/502707

Abstract: Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.