公开(公告)号：US11646351B2

公开(公告)日：2023-05-09

申请号：US17146513

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/49 ,  H01L29/47 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US20220223694A1

公开(公告)日：2022-07-14

申请号：US17146513

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US11177345B1

公开(公告)日：2021-11-16

申请号：US16893855

申请日：2020-06-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Henry L. Aldridge, Jr. ,  Anthony K. Stamper ,  Jeonghyun Hwang ,  Johnatan A. Kantarovsky

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/417 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first semiconductor layer including a device region; a second semiconductor layer under the first semiconductor layer; a layer of conductive material between the first semiconductor layer and the second semiconductor layer; at least one contact extending to and contacting the layer of conductive material; and a device in the device region above the layer of conductive material.

公开(公告)号：US20250072024A1

公开(公告)日：2025-02-27

申请号：US18237195

申请日：2023-08-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alvin J. Joseph ,  Mark D. Levy ,  Rajendran Krishnasamy ,  Johnatan A. Kantarovsky ,  Ajay Raman ,  Ian A. McCallum-Cook

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/45 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a thermal plug and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a thermal plug extending from a top side of the semiconductor substrate into an active region of the semiconductor substrate.

公开(公告)号：US12046633B2

公开(公告)日：2024-07-23

申请号：US17157269

申请日：2021-01-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Vibhor Jain

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/764 ,  H01L27/06 ,  H01L27/07 ,  H01L29/08

CPC classification number: H01L29/0657 ,  H01L21/308 ,  H01L21/764 ,  H01L27/0635 ,  H01L27/0755 ,  H01L29/0653 ,  H01L29/0821

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

公开(公告)号：US20230037420A1

公开(公告)日：2023-02-09

申请号：US17386062

申请日：2021-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Brett T. Cucci ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

公开(公告)号：US11574867B2

公开(公告)日：2023-02-07

申请号：US17104078

申请日：2020-11-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/8249 ,  H01L21/02 ,  H01L27/07 ,  H01L23/62 ,  H01L27/115 ,  H01L27/112 ,  H01L27/02

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US20220165663A1

公开(公告)日：2022-05-26

申请号：US17104078

申请日：2020-11-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC: H01L23/525 ,  H01L27/07 ,  H01L21/02 ,  H01L21/8249

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US20250142860A1

公开(公告)日：2025-05-01

申请号：US18385255

申请日：2023-10-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven J. Bentley ,  Santosh Sharma ,  Johnatan A. Kantarovsky ,  Mark D. Levy ,  Michael J. Zierak

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a gate structure; a first barrier layer under and adjacent to the gate structure; and a second barrier layer over the first barrier layer and which is adjacent to the gate structure.

公开(公告)号：US20250120155A1

公开(公告)日：2025-04-10

申请号：US18376668

申请日：2023-10-04

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Johnatan A. Kantarovsky ,  Michael J. Zierak ,  Santosh Sharma ,  Steven J. Bentley

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a semiconductor substrate; at least one insulator film over the semiconductor substrate, the at least one insulator film including a recess; and a field plate extending into the at least one recess and over the at least one insulator film.