公开(公告)号：JP2004192615A

公开(公告)日：2004-07-08

申请号：JP2003380473

申请日：2003-11-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  GHAI SANJEEV ,  WRIGHT KENNETH LEE

IPC: G06F3/06 ,  G06F12/00 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0802 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/10

Abstract: PROBLEM TO BE SOLVED: To disclose a hardware management virtual-physical address conversion mechanism for a data processing system having no system memory.
SOLUTION: The data processing system includes a plurality of processors. The processors have volatile cache memories to be operated in a virtual address space larger than an actual address space. The processors and the respective volatile memories are connected with a storage controller 25 to be operated in a physical address space. The processors and the storage controller 25 are connected with a hard disk 102 via mutual connection. a virtual-physical conversion table for converting a virtual address in one volatile cache memory among the volatile cache memories into a physical disk address pointing a storage location in the hard disk without interposing the actual address is stored in the hard disk 102.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2003067357A

公开(公告)日：2003-03-07

申请号：JP2002170907

申请日：2002-06-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  FIELDS JAMES STEPHEN JR

IPC: G06F12/08 ,  G06F12/10 ,  G06F13/14 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177

CPC classification number: G06F12/0888 ,  G06F12/0813

Abstract: PROBLEM TO BE SOLVED: To provide a nonuniform memory access (NUMA) data processing system without unnecessary coherency communication. SOLUTION: This NUMA data processing system 10 comprises a plurality of nodes 12. Each of these nodes 12 comprises a plurality of processing devices 14 and at least one system memory 26 having a page table. The table comprises at least one entry used for converting a group of non-physical addresses into physical addresses. The entry specifies control information belonging to the group of non-physical addresses for each node 12, and comprises at least one data storage control field. The field comprises a plurality of write through indicators linked to the plurality of nodes 12. When the indicators are set, the processing device 14 in the related node 12 does not cache the altered data but is returned to the system memory in the home node by writing.

Abstract translation: 要解决的问题：提供不一致的存储器访问（NUMA）数据处理系统，而不需要不必要的一致性通信。 解决方案：该NUMA数据处理系统10包括多个节点12.这些节点12中的每一个包括多个处理装置14和至少一个具有页表的系统存储器26。 该表包括用于将一组非物理地址转换成物理地址的至少一个条目。 条目指定属于每个节点12的非物理地址组的控制信息，并且包括至少一个数据存储控制字段。 该字段包括链接到多个节点12的多个写通指示符。当指示符被设置时，相关节点12中的处理装置14不缓存改变的数据，而是通过在家节点中的系统存储器返回 写作。

公开(公告)号：JP2003044456A

公开(公告)日：2003-02-14

申请号：JP2002164472

申请日：2002-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  FIELDS JAMES STEPHEN JR

IPC: G06F12/08 ,  G06F15/177

CPC classification number: G06F12/0817 ,  G06F2212/2542

Abstract: PROBLEM TO BE SOLVED: To provide a NUMA architecture for improving memory access time in exclusive access operation. SOLUTION: A NUMA computer system 50 has at least two nodes 52 coupled by a node interconnect switch 55. Each of nodes 52 is equal and is provided with at least one processing unit 54 coupled to a local interconnect 58 and a node controller 56 coupled between the local interconnect 58 and the node interconnect switch 55. Each of node controllers 56 is functioned as a local agent for the other node 52 by transmitting a selecting instruction received on the local interconnect 58 through the node interconnect 55 to the other node 52 and transmitting the received selecting instruction to the local interconnect 58.

Abstract translation: 要解决的问题：提供一种NUMA架构，用于改进独占访问操作中的存储器访问时间。 解决方案：NUMA计算机系统50具有由节点互连开关55耦合的至少两个节点52.节点52中的每一个相等并且设置有耦合到局部互连58和节点控制器56的至少一个处理单元54， 局部互连58和节点互连交换机55.每个节点控制器56通过将通过节点互连55在本地互连58上接收的选择指令发送到另一个节点52并发送 接收到的选择指令到本地互连58。

公开(公告)号：JP2003044455A

公开(公告)日：2003-02-14

申请号：JP2002164228

申请日：2002-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  FIELDS JAMES STEPHEN JR

IPC: G06F12/08 ,  G06F15/177 ,  G06F15/16 ,  G06F15/167

CPC classification number: G06F12/0817 ,  G06F2212/2542

Abstract: PROBLEM TO BE SOLVED: To provide a NUMA architecture having improved queuing, storage and communication functions. SOLUTION: A NUMA computer system 50 has at least two nodes 52 coupled by a node interconnect switch 55. Each of nodes 52 is equal and is coupled between a processing unit 54 coupled to a local interconnect 58 and the node interconnect switch 55. A node controller 56 is functioned as a local agent for the other node 52 by transmitting a selecting instruction received on the local interconnect 58 onto the local interconnect 58 by transmitting the received selecting instruction through the node interconnect switch 55 to the other node 52.

Abstract translation: 要解决的问题：提供具有改进的排队，存储和通信功能的NUMA架构。 解决方案：NUMA计算机系统50具有由节点互连开关55耦合的至少两个节点52.节点52中的每一个相等并且耦合在耦合到局部互连58的处理单元54和节点互连开关55之间。节点 通过将接收到的选择指令通过节点互连交换机55发送到另一个节点52，控制器56通过将本地互连58上接收的选择指令发送到本地互连58来用作另一个节点52的本地代理。

公开(公告)号：JP2003030169A

公开(公告)日：2003-01-31

申请号：JP2002164275

申请日：2002-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  FIELDS JAMES STEPHEN JR

IPC: G06F12/08 ,  G06F15/177

CPC classification number: G06F12/0817

Abstract: PROBLEM TO BE SOLVED: To provide a non-uniform memory access(NUMA) architecture having improved queuing, storage communication efficiency.
SOLUTION: A non-uniform memory access(NUMA) computer system includes a first node and a second node coupled by a node interconnect. The second node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, and a controller coupled to the local interconnect. In response to snooping an operation from the first node issued on the local interconnect by the node controller, the controller signals acceptance of responsibility for coherency management activities related to the operation in the second node required by the operation, and thereafter provides notification of performance of the coherency management activities. In order to promote the efficient utilization of queues within the node controller, the node controller preferably allocates a queue to the operation in response to receipt of the operation from the node interconnect, and then deallocates the queue in response to transferring responsibility for coherency management activities to the controller.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供具有改进的排队，存储通信效率的不均匀的存储器访问（NUMA）架构。 解决方案：非均匀存储器访问（NUMA）计算机系统包括通过节点互连耦合的第一节点和第二节点。 第二节点包括本地互连，耦合在本地互连和节点互连之间的节点控制器以及耦合到本地互连的控制器。 响应于从节点控制器在本地互连上发出的来自第一节点的操作，控制器指示接受与操作所需的第二节点中的操作有关的一致性管理活动的责任，并且此后提供对 一致性管理活动。 为了促进节点控制器内的队列的有效利用，节点控制器优选地响应于从节点互连接收到的操作而为该操作分配队列，然后响应于对相干性管理活动的转移责任而释放队列 到控制器。

公开(公告)号：JPH11328140A

公开(公告)日：1999-11-30

申请号：JP3144599

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  DEREK EDWARD WILLIAMS ,  LEWIS JERRY DON

IPC: G06F15/177 ,  G06F9/52 ,  G06F12/08 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To synchronize processings in a multiprocessor system by filter- interrupting unnecessary synchronous bus operations before sending them out onto a system bus based on history instruction execution information. SOLUTION: An instruction is received from local processors 102 and 104, and whether or not the received instruction is an architected instruction for urging the operation of a system bus 122 with the possibility of affecting data storage in another device inside the multiprocessor system 100 is judged. In the case of the architected instruction by the judgement, an unnecessary synchronous operation is filter-interrupted by using history information relating to an architected operation requiring the transmission of the synchronous operation to the system bus 122. Thus, processings in the multiprocessor system 100 are synchronized.

公开(公告)号：JPH11328023A

公开(公告)日：1999-11-30

申请号：JP3150399

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain an improved method and device to process a snooping operation in a multi-processor system. SOLUTION: When a device which snoops around a system bus 122 detects an operation which requests data resident in a local memory in a certain coherency state, the device tries intervention. If this intervention is hindered by a second device which asserts retry, the device sets a flag which provides activity record information related to the intervention where a hindrance occurs. When the device asserts the intervention again and the snooped operation is retried again at the time of a following snoop hit to the same cache position, the device takes a measure to change the coherency state of a requested cache item to the final coherency state which is expected to be the result of the original operation requesting the cache item.

公开(公告)号：JPH11328017A

公开(公告)日：1999-11-30

申请号：JP6038299

申请日：1999-03-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To realize a cache directory addressing and parity check system which reduces the data storage size for cache in a data processing system. SOLUTION: The index field of an address is mapped to lower-order cache directory address lines. The other cache directory address line, namely, the highest-order line is indexed by parity of an address tag for a cache entry to be stored in a corresponding cache directory entry or a cache entry to be retrieved from the corresponding cache directory entry. Consequently, an even parity address tag is stored in a cache directory location which has '0' in the most significant index/address bit (msb), and an odd parity address tag is stored in a cache directory location which has '1' in the most significant index/address bit.

公开(公告)号：JPH11272557A

公开(公告)日：1999-10-08

申请号：JP2664399

申请日：1999-02-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

CPC classification number: G06F12/0815

Abstract: PROBLEM TO BE SOLVED: To avoid an unnecessary write operation to a system memory by maintaining cache coherence in a multiprocessor computer system through the use of a coherence state with tag.
SOLUTION: When a changed value is allocated to a cache line which is loaded most recently, a state with tag can be moved by crossing a cache in a horizontal direction. When a request is given for accessing to a block, related priority is given so that only a response having the highest priority is sent to a requesting processing unit. When a cache block is in a change state in one processor and a read operation is requested by the different processor, the first processor sends a change intervention response and a read processor can hold the data in a T state.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过使用具有标签的相干状态，通过维持多处理器计算机系统中的高速缓存一致性来避免对系统存储器的不必要的写入操作。 解决方案：当将更改的值分配给最近加载的高速缓存行时，可以通过在水平方向上跨越高速缓存来移动具有标签的状态。 当给出访问块的请求时，给出相关的优先级，使得只有具有最高优先级的响应被发送到请求处理单元。 当缓存块在一个处理器中处于改变状态并且由不同处理器请求读取操作时，第一处理器发送改变干预响应，并且读取处理器可以将数据保存在T状态。

公开(公告)号：JP2004326808A

公开(公告)日：2004-11-18

申请号：JP2004131849

申请日：2004-04-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  FLOYD MICHAEL STEPHEN ,  REICK KEVIN FRANKLIN

IPC: G06F13/14 ,  G06F9/445 ,  G06F13/00 ,  G06F13/12 ,  G06F13/40 ,  G06F15/16 ,  G06F15/177

CPC classification number: G06F13/4081

Abstract: PROBLEM TO BE SOLVED: To provide a data processing system having a function of adding and removing a hot plug of individual hot plug possible constitution elements without intervening it to a present operation of a whole processing system. SOLUTION: The processing system includes a mutual connection structure including a hot plug connector which can connect the outer hot plug possible constitution element to the data processing system. A logical constitution element includes constitution logic, routing and operation logic. When the hot plug possible constitution element is connected to the hot plug connector, a service element automatically detects connection and selects a correct constitution file for an extension system. When the constitution file is once loaded and that the operation of the new element is prepared is shown by system check of the new element, the new element is integrated in the existed system. OS allocates a work load to the new element. The whole processes are performed without turning off power or without intervening it to the operation of the existed element from a viewpoint of a customer. COPYRIGHT: (C)2005,JPO&NCIPI