公开(公告)号：CA2548085C

公开(公告)日：2014-04-29

申请号：CA2548085

申请日：2004-12-08

Applicant: IBM

Inventor： BIRAN GIORA ,  MACHULSKY ZORIK ,  MAKHERVAKS VADIM ,  SHALEV LEAH

IPC: H04L1/22 ,  H03M13/09 ,  H04L29/08

Abstract: A network interface controller implementation that performs direct data placement to memory where all segments of a particular connection are aligned, i.e. cuts-through without accessing reassembly buffers (i.e., a "Fast" connection type), or if all segments are non~aligned moves data through reassembly buffers (i.e., a "Slow" connection type). The type of connection can change from Fast to Slow and back. The implementation preferably conducts CRC validation for a majority of inbound DDP segments in the Fast connection before sending a TCP acknowledgement confirming segment reception. The method of computing a CRC value according to the present invention assumes that each TCP segment starts with an aligned DDP segment and that the first two bytes of a TCP payload is an MPA length field of an MPA frame.

公开(公告)号：CA2548085A1

公开(公告)日：2005-07-07

申请号：CA2548085

申请日：2004-12-08

Applicant: IBM

Inventor： SHALEV LEAH ,  MAKHERVAKS VADIM ,  MACHULSKY ZORIK ,  BIRAN GIORA

IPC: H04L1/22 ,  H04L29/08

Abstract: A network interface controller implementation that performs direct data placement to memory where all segments of a particular connection are aligne d, i.e. cuts-through without accessing reassembly buffers (i.e., a "Fast" connection type), or if all segments are non~aligned moves data through reassembly buffers (i.e., a "Slow" connection type). The type of connection can change from Fast to Slow and back. The implementation preferably conduct s CRC validation for a majority of inbound DDP segments in the Fast connection before sending a TCP acknowledgement confirming segment reception. The metho d of computing a CRC value according to the present invention assumes that eac h TCP segment starts with an aligned DDP segment and that the first two bytes of a TCP payload is an MPA length field of an MPA frame.

公开(公告)号：HU0302879A2

公开(公告)日：2003-12-29

申请号：HU0302879

申请日：2001-01-31

Applicant: IBM

Inventor： BIRAN GIORA ,  SOSTHEIM TAL

IPC: G06F13/00 ,  G06F13/40 ,  H04L12/26 ,  H04L12/56

Abstract: Apparatus, methods and systems for controlling data flow between data processing systems. In an example embodiment, the apparatus includes descriptor logic for generating a plurality of descriptors including a frame descriptor defining a data packet to be communicated between a location in the memory and a data processing system, and a pointer descriptor identifying the location in the memory. The apparatus also includes a descriptor table for storing descriptors generated by the descriptor logic for access by the data processing systems.

公开(公告)号：CZ20032078A3

公开(公告)日：2003-11-12

申请号：CZ20032078

申请日：2001-01-31

Applicant: IBM

Inventor： BIRAN GIORA ,  SOSTHEIM TAL

IPC: G06F13/00 ,  G06F13/40 ,  H04L12/26 ,  H04L12/56

Abstract: Apparatus, methods and systems for controlling data flow between data processing systems. In an example embodiment, the apparatus includes descriptor logic for generating a plurality of descriptors including a frame descriptor defining a data packet to be communicated between a location in the memory and a data processing system, and a pointer descriptor identifying the location in the memory. The apparatus also includes a descriptor table for storing descriptors generated by the descriptor logic for access by the data processing systems.

公开(公告)号：CA2432390A1

公开(公告)日：2002-08-08

申请号：CA2432390

申请日：2001-01-31

Applicant: IBM

Inventor： SOSTHEIM TAL ,  BIRAN GIORA

IPC: G06F13/00 ,  G06F9/46 ,  G06F13/14 ,  G06F13/40

Abstract: Apparatus for controlling flow of data between a memory of a host computer system and a data communications interface for communicating data between th e host computer system and a data communications network is described. The apparatus comprises a descriptor table for storing a plurality of descriptor s for access by the host computer system and data communications interface. Descriptor logic generates the descriptors for storage in the descriptor table. The descriptors include a branch descriptor comprising a link to another descriptor in the table.

公开(公告)号：CA2432386A1

公开(公告)日：2002-08-08

申请号：CA2432386

申请日：2001-01-31

Applicant: IBM

Inventor： BIRAN GIORA ,  MACHULSKY GEORGY ,  SCHILLER CLAUDIU ,  SOSTHEIM TAL

IPC: G06F3/00 ,  G06F13/24

Abstract: Apparatus for transferring interrupts form a peripheral device to a host computer system is described. The apparatus comprises a buffer for storing indications of interrupts generated by the peripheral device. In response to a preset condition being met, a controller generates a control data block havi ng a payload portion, moves the contents of the buffer to the payload poriton o f the control data block, and sends the control data block to the host compute r system.