公开(公告)号：JP2008124457A

公开(公告)日：2008-05-29

申请号：JP2007278059

申请日：2007-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7856

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetric multi gate transistor and its forming method. SOLUTION: The asymmetric multi gate transistor comprises a semiconductor fin having uneven doping profile in one embodiment. A first portion of the fin has a richer doping concentration, while a second portion of the fin has a thinner doping concentration. In another embodiment, such asymmetric multi gate transistor as comprises a gate dielectrics which is formed on the semiconductor fin and has a different thickness is disclosed. The asymmetric multi gate transistor comprises a thin gate dielectrics formed on the first side surface of the semiconductor fin and a thick gate dielectrics formed on the second side surface of the fin. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种非对称多栅极晶体管及其形成方法。 解决方案：在一个实施例中，非对称多栅极晶体管包括具有不均匀掺杂分布的半导体鳍片。 翅片的第一部分具有更丰富的掺杂浓度，而翅片的第二部分具有较薄的掺杂浓度。 在另一个实施例中，公开了这种非对称多栅极晶体管，其包括形成在半导体鳍片上并且具有不同厚度的栅极电介质。 非对称多栅极晶体管包括形成在半导体鳍片的第一侧表面上的薄栅极电介质和形成在鳍片的第二侧表面上的厚栅极电介质。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007258693A

公开(公告)日：2007-10-04

申请号：JP2007039465

申请日：2007-02-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO

IPC: H01L21/3065

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of recessing trenches to a target depth by using feed forward data. SOLUTION: A method of recessing trenches by using feed forward data is disclosed. In one embodiment, the method comprises: a step of providing a region on a wafer, which includes a trench area 20 having trenches 22 and a field area 24 having no trenches, and over which a material is applied so as to fill the trenches in the trench area and to form difference in level between the trench area and the field area; a step of partially etching the trenches; a step of determining a target etch duration for etching to a target depth D T ; and a step of etching the trenches to the target depth D T for a period approximately equal to the target etch duration. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供通过使用前馈数据将沟槽凹陷到目标深度的方法。 公开了一种通过使用前馈数据使沟槽凹陷的方法。 在一个实施例中，该方法包括：在晶片上提供区域的步骤，该区域包括具有沟槽22的沟槽区域20和不具有沟槽的场区域24，并且在其上施加材料以填充沟槽 沟渠区域，并形成沟槽区域和场地区域之间的水平差异; 部分蚀刻沟槽的步骤; 确定蚀刻到目标深度D 的目标蚀刻持续时间的步骤; 以及在大约等于目标蚀刻持续时间的时间内将沟槽蚀刻到目标深度D T 的步骤。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2005094005A

公开(公告)日：2005-04-07

申请号：JP2004266297

申请日：2004-09-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMA ,  GLUSCHENKOV OLEG G

IPC: H01L21/8242 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure of a vertical strained silicon device.
SOLUTION: A trench capacitor vertical-transistor DRAM cell in an SiGe wafer compensates for overhang of a pad nitride, by forming an epitaxial strained silicon layer on trench walls that improves transistor mobility, removes voids from the polysilicon filling, and reduces resistance on the bit line contact. Another feature is that by forming a vertical strained silicon channel, the performance of the vertical device is improved.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供垂直应变硅器件的方法和结构。 解决方案：SiGe晶片中的沟槽电容器垂直晶体管DRAM单元通过在沟槽壁上形成外延应变硅层来补偿衬垫氮化物的突出，从而提高晶体管的迁移率，去除多晶硅填充物的空隙，并降低电阻 在位线上联系。 另一个特征是通过形成垂直应变硅通道，提高了垂直装置的性能。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2013115427A

公开(公告)日：2013-06-10

申请号：JP2012196345

申请日：2012-09-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： THEODORUS EDUARDUS STANDAERT ,  BALASUBRAMANIAN S HARAN ,  CHENG KANGGUO ,  SHOM PONOTH ,  YAMASHITA TENKO ,  SEO SOON-CHEON

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC classification number: H01L29/6681 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a FinFET which is improved in flatness of a gate.SOLUTION: The gate is arranged on a pattern of fins before unnecessary fins are removed. The unnecessary fins can be removed by using a lithography technique, an etching technique, or a combination of them. All or some of the remaining fins can be merged.

Abstract translation: 要解决的问题：提供一种形成FinFET的方法，该FinFET在栅极的平坦度方面得到改善。 解决方案：在不必要的散热片被去除之前，门被布置在鳍状图案上。 可以通过使用光刻技术，蚀刻技术或它们的组合来去除不需要的散热片。 所有或一些剩余的鳍可以合并。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2007123875A

公开(公告)日：2007-05-17

申请号：JP2006284413

申请日：2006-10-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  GREENE BRIAN J ,  MANDELMAN JACK ALLAN

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L21/76245 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a germanium-on-insulator semiconductor structure using a porous layer, and a semiconductor structure formed by the method.
SOLUTION: This semiconductor structure comprises a layer containing a single crystal germanium which is preferably substantially pure germanium, a substrate and an embedded insulating layer for separating the layer containing germanium from the substrate. A porous layer which can be converted into a porous silicone layer is formed on the substrate and the layer containing germanium is formed on the porous silicone layer. By converting the porous layer into an oxide layer, an embedded insulating layer can be formed. Alternatively, the layer containing germanium on the porous layer can be moved to an insulating layer on another substrate. After moved, an insulating layer is embedded between the later substrate and the layer containing germanium.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用多孔层形成绝缘体上的锗锗的方法，以及通过该方法形成的半导体结构。 解决方案：该半导体结构包括含有优选基本上纯锗的单晶锗的层，用于将含锗层与基板分离的衬底和嵌入绝缘层的层。 在基材上形成能够转化为多孔硅酮层的多孔层，在多孔硅树脂层上形成含锗层。 通过将多孔层转化为氧化物层，可以形成嵌入绝缘层。 或者，可以在多孔层上含有锗的层移动到另一基底上的绝缘层。 移动后，在后面的基板和含有锗的层之间嵌入绝缘层。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005051246A

公开(公告)日：2005-02-24

申请号：JP2004222267

申请日：2004-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDORA DEIVAKARUNI ,  SUNG C Y

IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02

CPC classification number: H01L27/10876 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/1087 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for a vertical DRAM device having a self-aligning function of shaping upper trench. SOLUTION: The method and the structure of a memory storage cell in a semiconductor substrate include forming of a dopant source material, covering a lower portion of a deep trench formed in the substrate. The upper portion of the trench is generally shaped into a rectangular form, and an embedded electrode plate of a trench capacitor by annealing the dopant source material. The embedded electrode plate is self-aligned, with respect to the shaped upper-portion of the trench. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供一种具有成形上沟槽自对准功能的垂直DRAM器件的方法和结构。 解决方案：半导体衬底中的存储器存储单元的方法和结构包括形成掺杂剂源材料，覆盖形成在衬底中的深沟槽的下部。 沟槽的上部通常通过对掺杂剂源材料进行退火而成形为矩形形状，以及沟槽电容器的嵌入式电极板。 嵌入式电极板相对于沟槽的成形上部自对准。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005019994A

公开(公告)日：2005-01-20

申请号：JP2004183609

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDORA DEIVAKARUNI

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/3215 ,  H01L27/1087

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a buried plate in a trench capacitor, thereby overcoming limitation in the conventional method.
SOLUTION: A dopant source material such as ASG is completely filled into a trench. Next, a recess is formed on this dopant source material, and a collar material is deposited thereon. Thus, a collar is formed on the upper side portion of the trench. After the buried plate is formed through drive-in of the dopant, the dopant source material is removed and the collar material may be removed.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在沟槽电容器中形成掩埋板的方法，从而克服了常规方法中的限制。 解决方案：诸如ASG的掺杂剂源材料被完全填充到沟槽中。 接下来，在该掺杂剂源材料上形成凹部，并且在其上沉积套环材料。 因此，在沟槽的上侧部分上形成有套环。 在通过掺杂剂的驱入形成掩埋板之后，去除掺杂剂源材料并且可以去除套环材料。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2011037743A3

公开(公告)日：2011-07-07

申请号：PCT/US2010048039

申请日：2010-09-08

Applicant: IBM ,  CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE B ,  SHAHIDI GHAVAM

Inventor： CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE B ,  SHAHIDI GHAVAM

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack (18), e.g., FET, located on an upper surface (14) of a semiconductor substrate (12). The structure further includes a first epitaxy semiconductor material (34) that induces a strain upon a channel (40) of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions (28) in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region (38) is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material (36) located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

Abstract translation: 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底（12）的上表面（14）上的至少一个栅叠层（18），例如FET。 该结构还包括在至少一个栅极堆叠的沟道（40）上引起应变的第一外延半导体材料（34）。 所述第一外延半导体材料位于所述至少一个栅极堆叠的基准面上，基本上位于所述衬底中的存在于所述至少一个栅极叠层的相对侧上的一对凹陷区域（28）内。 扩散延伸区域（38）位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散延伸区域的上表面上的第二外延半导体材料（36）。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

公开(公告)号：WO2007115002A3

公开(公告)日：2008-11-06

申请号：PCT/US2007064380

申请日：2007-03-20

Applicant: IBM ,  DIVAKARUNI RAMACHANDRA ,  CHENG KANGGUO

Inventor： DIVAKARUNI RAMACHANDRA ,  CHENG KANGGUO

IPC: H01L21/44 ,  C01B32/50 ,  H01L21/00

CPC classification number: H01L29/7827 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of forming a body contact (215) for an semiconductor-on-insulator trench device. The method including: forming set of mandrels (190) on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers (195) on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening (197) in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench (200) in the substrate in the opening; and filling the contact trench with an electrically conductive material (210) to form the contact.

Abstract translation: 一种形成用于绝缘体上半导体沟槽器件的体接触（215）的结构和方法。 该方法包括：在基板的顶表面上形成一组心轴（190），该心轴组的每个心轴布置在多边形的不同角上并在衬底的顶表面上方延伸， 一组心轴等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件（195），每个相邻的一对心轴的侧壁间隔件彼此合并并形成在多边形的内部区域中限定开口（197）的不间断的壁，区域 的基板暴露在开口中; 蚀刻开口中的衬底中的接触沟槽（200）; 以及用导电材料（210）填充所述接触沟槽以形成所述接触。

公开(公告)号：WO2007082200A3

公开(公告)日：2008-07-03

申请号：PCT/US2007060266

申请日：2007-01-09

Applicant: IBM ,  CHENG KANGGUO ,  RASSEL ROBERT M

Inventor： CHENG KANGGUO ,  RASSEL ROBERT M

IPC: H01L29/94

CPC classification number: H01L29/945 ,  H01L27/016 ,  H01L27/0682 ,  H01L28/20 ,  H01L29/66181

Abstract: A structure and a method for fabrication of the structure use a capacitor trench (CT) for a trench capacitor and a resistor trench (RT) for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench (CT) has a linewidth dimension (LWC) narrower than the resistor trench (RT). The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material (18a, 18b) at a periphery of the resistor trench (RT) and a resistor material (20) at a central portion of the resistor trench (RT).

Abstract translation: 用于制造结构的结构和方法使用用于沟槽电容器的电容器沟槽（CT）和用于沟槽电阻器的电阻器沟槽（RT）。 该结构通常是半导体结构。 在第一种情况下，电容器沟槽（CT）具有比电阻器沟槽（RT）窄的线宽尺寸（LWC）。 沟槽线宽差提供了制造沟槽电容器和沟槽电阻器的有效方法。 在第二种情况下，沟槽电阻器包括在电阻器沟槽（RT）的外围的导体材料（18a，18b）和电阻器沟槽（RT）的中心部分处的电阻材料（20）。