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    A SCHOTTKY BARRIER DIODE, A METHOD OF FORMING THE DIODE AND A DESIGN STRUCTURE FOR THE DIODE
    1.
    发明申请
    A SCHOTTKY BARRIER DIODE, A METHOD OF FORMING THE DIODE AND A DESIGN STRUCTURE FOR THE DIODE 审中-公开
    肖特基势垒二极管，形成二极管的方法和二极管的设计结构

    公开(公告)号：WO2012106101A2

    公开(公告)日：2012-08-09

    申请号：PCT/US2012/021483

    申请日：2012-01-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  RASSEL, Robert, M. ,  STIDHAM, Mark, E.

    Inventor： RASSEL, Robert, M. ,  STIDHAM, Mark, E.

    IPC: H01L29/872 ,  H01L21/328

    CPC classification number: H01L29/66143 ,  G06F17/5068 ,  H01L29/872

    Abstract: Disclosed are embodiments of a Schottky barrier diode (100). This Schottky barrier diode can be formed in a semiconductor substrate (101) having a doped region (110) with a first conductivity type. A trench isolation structure (120) can laterally surround a section (111) of the doped region at the top surface (102) of the substrate. A semiconductor layer (150) can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion (151) over the defined section (111) of the doped region and a guardring portion (152) over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer (140) can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.

    Abstract translation: 公开了肖特基势垒二极管（100）的实施例。 该肖特基势垒二极管可以形成在具有第一导电类型的掺杂区域（110）的半导体衬底（101）中。 沟槽隔离结构（120）可横向包围衬底的顶表面（102）处的掺杂区域的部分（111）。 半导体层（150）可以位于衬底的顶表面上。 该半导体层可以具有在掺杂区的限定部分（111）上方的肖特基势垒部分（151）和在肖特基势垒部分的侧向包围的沟槽隔离结构上的防护部分（152）。 肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。 金属硅化物层（140）可以覆盖半导体层。 还公开了形成该肖特基势垒二极管的方法和用于肖特基势垒二极管的设计结构的实施例。

    INTERLEVEL CONDUCTIVE LIGHT SHIELD
    2.
    发明申请
    INTERLEVEL CONDUCTIVE LIGHT SHIELD 审中-公开
    交互式导光灯

    公开(公告)号：WO2009149221A1

    公开(公告)日：2009-12-10

    申请号：PCT/US2009/046188

    申请日：2009-06-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GAMBINO, Jeffrey, P. ,  HE, Zhong-xiang ,  OGG, Kevin, N. ,  RASSEL, Richard, J. ,  RASSEL, Robert, M.

    Inventor： GAMBINO, Jeffrey, P. ,  HE, Zhong-xiang ,  OGG, Kevin, N. ,  RASSEL, Richard, J. ,  RASSEL, Robert, M.

    IPC: G01J1/42

    CPC classification number: H01L27/14623 ,  H01L27/1463 ,  H01L27/14632

    Abstract: A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure The conductive light shiel covers a floating drain of an image sensor pixel cell A second dielectric layer is formed over the conductive light shield and at least on via extending from a top surface of the second dielectnic layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

    Abstract translation: 在金属互连结构中的通孔电平的第一电介质层上形成导电屏蔽。导电光罩覆盖图像传感器像素单元的浮动漏极。第二介电层形成在导电光屏蔽上，并且至少在通孔 在金属互连结构中形成从第二介电层的顶表面延伸到第一电介质层的底表面。导电屏蔽可以形成在半导体衬底的顶表面和第一金属线之间的接触电平内 或者可以通过两个金属线路电平之间的电平形成在任何金属互连中。由于通过导电光屏蔽而在浮动漏极上阻挡光，本发明的图像传感器像素单元不太容易产生噪声。

    DEEP TRENCH VARACTORS
    3.
    发明申请
    DEEP TRENCH VARACTORS 审中-公开

    公开(公告)号：WO2010075052A1

    公开(公告)日：2010-07-01

    申请号：PCT/US2009/067972

    申请日：2009-12-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COLLINS, David, S. ,  RASSEL, Robert, M. ,  THOMPSON, Eric

    Inventor： COLLINS, David, S. ,  RASSEL, Robert, M. ,  THOMPSON, Eric

    IPC: H01L29/93

    CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L27/0808 ,  H01L29/66181 ,  H01L29/945

    Abstract: A deep trench varactor structure (3OA, 4OA, 50) compatible with a deep trench capacitor structure (20, 30B, 40B) and methods of manufacturing the same are provided. A buried plate layer (20) is formed on a second deep trench (HB), while the first trench (1 IA) is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes (4OA, 40B). At least one doped well (50) is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells (50, 60) may be connected in parallel to provide a varactor (30A, 4OA, 50, 60) having complex voltage dependency of capacitance. The buried plate layer and another doped well (52) connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.

    Abstract translation: 提供了与深沟槽电容器结构（20,30B，40B）兼容的深沟槽变容二极管结构（30A，40A，50）及其制造方法。 掩埋板层（20）形成在第二深沟槽（HB）上，而第一沟槽（11A）被保护而不形成任何掩埋的板层。 深沟槽的内部填充有导电材料以形成内部电极（40A，40B）。 至少一个掺杂阱（50）形成在第一深沟槽的外部和邻接部分上，并且构成至少一个外变容二极管电极。 多个掺杂阱（50,60）可以并联连接以提供具有复杂的电容电压依赖性的变容二极管（30A，40A，50,60）。 掩埋板层和与其连接的另一个掺杂阱（52）构成形成在第二深沟槽上的线性电容器的外部电极。

    AN INTEGRATED CIRCUIT STRUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM
    4.
    发明申请
    AN INTEGRATED CIRCUIT STRUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM 审中-公开
    一个集成电路结构，一个电感器，一个相关的设计方法和一个相关的设计系统

    公开(公告)号：WO2008121619A1

    公开(公告)日：2008-10-09

    申请号：PCT/US2008/058148

    申请日：2008-03-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HE, Zhong-Xiang ,  RASSEL, Robert, M. ,  VOLDMAN, Steven, H.

    Inventor： HE, Zhong-Xiang ,  RASSEL, Robert, M. ,  VOLDMAN, Steven, H.

    IPC: H01L23/62

    CPC classification number: G06F17/5063 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., Ml). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

    Abstract translation: 公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。 在电路中，ESD器件被连线到第一金属电平（例如M1）。 电感器形成在第一金属层上方的第二金属层（例如M5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。 对于给定的应用频率，电感器被配置为使ESD器件的电容值无效。 通过在第二金属层与第一金属层之间的第三金属层（例如M3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。 屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

    SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION
    7.
    发明申请
    SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION 审中-公开
    肖特基二极管与周边电容良好连接

    公开(公告)号：WO2012012157A2

    公开(公告)日：2012-01-26

    申请号：PCT/US2011/042296

    申请日：2011-06-29

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ANDERSON, Frederick, G. ,  LARY, Jenifer, E. ,  RASSEL, Robert, M. ,  STIDHAM, Mark, E.

    Inventor： ANDERSON, Frederick, G. ,  LARY, Jenifer, E. ,  RASSEL, Robert, M. ,  STIDHAM, Mark, E.

    IPC: H01L29/872 ,  H01L29/47

    CPC classification number: H01L29/872 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/66143

    Abstract: A Schottky barrier diode comprises a first-type substrate (100), a second-type well isolation region (102) on the first-type substrate, and a first-type well region (110) on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring (106) is on the second-type well isolation region. A second-type well region (104) is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region (108) is on the second-type well region, and a first-type contact region (112) contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer (124) is on the first- type contact region and a second ohmic metallic layer (126) is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.

    Abstract translation: 肖特基势垒二极管包括第一类型衬底（100），第一类型衬底上的第二类型阱隔离区（102）和第二类型阱隔离区上的第一类型阱区（110）。 在这里的实施例中，被称为周边电容阱接合环（106）的特征在第二类型的隔离区域上。 第二类型井区域（104）位于第二类型井隔离区域上。 周边电容阱接合环位于第一类型阱区域和第二类型阱区域之间并分离。 第二类型接触区域（108）位于第二类型阱区域上，并且第一类型接触区域（112）接触第一类型阱区域的内部部分。 第一类型阱区域的内部位于第一类型接触区域的中心内。 另外，第一欧姆金属层（124）在第一类型接触区域上，第二欧姆金属层（126）位于第一类型阱区域上。 第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处接触第二欧姆金属层。

    JUNCTION FIELD EFFECT TRANSISTOR WITH A HYPERABRUPT JUNCTION
    9.
    发明申请
    JUNCTION FIELD EFFECT TRANSISTOR WITH A HYPERABRUPT JUNCTION 审中-公开
    具有高压接点的结型场效应晶体管

    公开(公告)号：WO2009003012A1

    公开(公告)日：2008-12-31

    申请号：PCT/US2008/068139

    申请日：2008-06-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ESHUN, Ebenezer, E. ,  JOHNSON, Jeffrey, B. ,  PHELPS, Richard, A. ,  RASSEL, Robert, M. ,  ZIERAK, Michael, L.

    Inventor： ESHUN, Ebenezer, E. ,  JOHNSON, Jeffrey, B. ,  PHELPS, Richard, A. ,  RASSEL, Robert, M. ,  ZIERAK, Michael, L.

    IPC: H01L29/80 ,  H01L21/338 ,  H01L29/812

    CPC classification number: H01L29/808 ,  H01L27/0617 ,  H01L27/098 ,  H01L29/36 ,  H01L29/66901

    Abstract: A junction field effect transistor (JFET) (Fig. 4) has a hyperabrupl junction laj cr (54) that functions as a channel of a JFFT. The hyperabrupt junction layer (54) is formed by two dopant profiles (50. 52) of opposite t}pes such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body ( 16) that is doped with the same type of dopants as the gate. This is in contrast with conventional JI7KTs that have a body that is doped with the opposite conductivity type as the gate. The body ( 16) may be electrically decoupled from (Figure 4, 10 and 30) the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate (Figure 8. 16 and 1 10). The capability to form a thin hyperabrupt junction layer (54) allows formation of a JFET in a semiconductor-on-insulator substrate (Figure 11. 210. 230).

    Abstract translation: 结型场效应晶体管（JFET）（图4）具有作为JFFT通道发挥功能的超级联结结点laj cr（54）。 超破裂结层（54）由相对的t} pes的两个掺杂剂轮廓（50.52）形成，使得一个掺杂剂浓度分布在另一个掺杂剂分布的尾端处具有峰值浓度深度。 通道的电压偏置由掺杂有与栅极相同类型的掺杂剂的体（16）提供。 这与传统的JI7KT相反，传统的JI7KT具有以与栅极相反的导电类型掺杂的主体。 主体（16）可以通过在主体和衬底之间形成的另一个反向偏置连接点或者在主体和衬底之间的掩埋导体层之间（图8,10和30）与衬底电气去耦合（图8,10和30） 和110）。 形成薄的超破坏结层（54）的能力允许在绝缘体上半导体衬底中形成JFET（图11,210,230）。

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