公开(公告)号：FR2316803A1

公开(公告)日：1977-01-28

申请号：FR7615569

申请日：1976-05-17

Applicant: IBM

Inventor： EICHELBERGER EDWARD B ,  ROBBINS GORDON J

IPC: H03K3/287 ,  H03K3/286 ,  H03K3/288 ,  H03K17/66 ,  H03K19/08

Abstract: Disclosed is a high performance logically hazard-free latch circuit compatible with TTL technology. The occurrence of both a clock and data signal provides an inverted data output signal at the output node which is fed back to the base electrode of a multi-emitter transistor. The output node then remains latched at the desired logic level until the occurrence of a subsequent clock signal. Also disclosed are techniques for improving the capabilities of the latch and for accepting additional clock and data inputs. The polarity-hold latch circuit disclosed herein is advantageously implemented in semiconductor integrated circuit technology.

公开(公告)号：DE2556822A1

公开(公告)日：1976-06-24

申请号：DE2556822

申请日：1975-12-17

Applicant: IBM

Inventor： EICHELBERGER EDWARD B

IPC: G11C29/00 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/02 ,  G11C29/12 ,  G11C29/20 ,  G11C7/00 ,  H01L29/76

公开(公告)号：CA700293A

公开(公告)日：1964-12-22

申请号：CA700293D

Applicant: IBM

Inventor： EICHELBERGER EDWARD B