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    WEIGHTED RANDOM PATTERN TESTING APPARATUS AND METHOD
    4.
    发明专利
    WEIGHTED RANDOM PATTERN TESTING APPARATUS AND METHOD 未知

    公开(公告)号：CA1241375A

    公开(公告)日：1988-08-30

    申请号：CA501737

    申请日：1986-02-12

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  LANGMAID ROGER N ,  LINDBLOOM ERIC ,  MOTIKA FRANCO ,  SINCHAK JOHN L ,  WAICUKAUSKI JOHN A

    IPC: G02B13/04 ,  G01R31/28 ,  G02B13/06

    Abstract: Weighted Random Pattern Testing Apparatus and Method A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

    METHOD OF PROPAGATION DELAY TESTING A LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM
    5.
    发明专利
    METHOD OF PROPAGATION DELAY TESTING A LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM 未知

    公开(公告)号：CA1075770A

    公开(公告)日：1980-04-15

    申请号：CA280451

    申请日：1977-06-13

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  MUEHLDORF EUGEN I ,  WALTHER RONALD G ,  WILLIAMS THOMAS W

    IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  G06F11/00

    Abstract: METHOD OF PROPAGATION DELAY TESTING A LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM Propagation delay testing is perfomed on a generalized and modular logic system that contains embedded arrays and can be used as arithmetic/logical/control unit in a digital computer or data processing system. Each such unit can be composed of combinatorial logic and storage circuitry. The storage circuitry may be of two types, randomly arranged latches, or arrays of storage cells. In the organization presented here the latches are arranged such that they have the capability of performing scan-in/scan-out operations independently of system control. Using this scan capability, the method of the invention provides for the state of the storage latches to be preconditioned and independent of prior circuit history. Selected propagation paths are sensitized by patterns from an automated test generator or designer supplied patterns. By alternating selected inputs and by applying proper timing control, propagation delay indications through the selected paths are obtained to determine delay behavior of the logic system. The above

    METHOD OF LEVEL SENSITIVE TESTING A FUNCTIONAL LOGIC SYSTEM
    7.
    发明专利
    METHOD OF LEVEL SENSITIVE TESTING A FUNCTIONAL LOGIC SYSTEM 未知

    公开(公告)号：CA989481A

    公开(公告)日：1976-05-18

    申请号：CA180726

    申请日：1973-09-11

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B

    IPC: G01R31/28 ,  G01R31/3185 ,  G06F9/40 ,  G06F11/22 ,  G06F11/24 ,  G06F11/273 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H03K3/037

    Abstract: Level sensitive testing is performed on a generalized and modular logic system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using this scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.

    HIGH PERFORMANCE LATCH CIRCUIT
    8.
    发明专利
    HIGH PERFORMANCE LATCH CIRCUIT 未知

    公开(公告)号：CA1076218A

    公开(公告)日：1980-04-22

    申请号：CA255367

    申请日：1976-06-21

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  ROBBINS GORDON J

    IPC: H03K3/286 ,  H03K3/287 ,  H03K3/288 ,  H03K17/66 ,  H03K19/08

    Abstract: HIGH PERFORMANCE LATCH CIRCUIT Disclosed is a high performance logically hazard-free latch circuit compatible with TTL technology. The occurrence of both a clock and data signal provides an inverted data output signal at the output node which is fed back to the base electrode of a multi-emitter transistor. The output node then remains latched at the desired logic level until the occurrence of a subsequent clock signal. Also disclosed are techniques for improving the capabilities of the latch and for accepting additional clock and data inputs. The polarity-hold latch circuit disclosed herein is advantageously implemented in semiconductor integrated circuit technology. .. . . . _ ..... .. . ...... .. . ~ . . . . . . . . . . . . .... ....... .... . . . . . .. . .

    HIGH DENSITY SEMICONDUCTOR CHIP ORGANIZATION
    9.
    发明专利
    HIGH DENSITY SEMICONDUCTOR CHIP ORGANIZATION 未知

    公开(公告)号：CA1061009A

    公开(公告)日：1979-08-21

    申请号：CA255043

    申请日：1976-06-16

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  ROBBINS GORDON J

    IPC: H01L21/822 ,  H01L21/331 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H01L29/73 ,  H03K19/173 ,  H01L27/10 ,  H01L29/06 ,  H01L23/48

    Abstract: HIGH DENSITY ARCHITECTURE FOR A SEMICONDUCTOR CHIP A semiconductor chip layout including a plurality of logic cells arranged in columns. A cell may encompass one of two different magnitudes of area in the chip; and each column contains only cells having the same area. The layout is particularly appropriate for level sensitive logic systems which utilize both combinatorial as well as sequential networks. The combinatorial (combinational) networks are less orderly and require a greater number of selectable input connections, hence more area, than the sequential circuits. The wide and narrow columnar architecture allows a much greater circuit packing density on a chip, resulting in a substantial increase in the number of circuits for a given chip area. Performance is also increased because of the reduced area required by the sequential circuits.

    LEVEL SENSITIVE LOGIC SYSTEM
    10.
    发明专利
    LEVEL SENSITIVE LOGIC SYSTEM 未知

    公开(公告)号：CA1005529A

    公开(公告)日：1977-02-15

    申请号：CA180787

    申请日：1973-09-11

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B

    IPC: G06F7/00 ,  G01R31/28 ,  G01R31/3185 ,  G06F9/40 ,  G06F11/22 ,  G06F11/273 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H03K3/037

    Abstract: A generalized and modular logic system for all arithmetic/logical units of a digital computer. Each arithmetic/logical unit of a computer is partitioned into sections formed of combinational logic networks and storage circuitry. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, non-overlapping, independent system clock trains are used to control the latches. A single-sided delay dependency is imparted to the system. The feedback connections from the respective latch circuitry are made through combinational logic to other latch circuitry that has a system clock other than the system clock acting on the initiating latch circuitry. With each latch, there is provided additional circuitry so that each latch acts as one position of a shift register having input/output and shift controls that are independent of the system clocks and the system inputs/outputs. All of the shift register latches are coupled together into a single shift register.

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