公开(公告)号：AT239944T

公开(公告)日：2003-05-15

申请号：AT00907775

申请日：2000-03-03

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES

IPC: G06F13/38 ,  G06F13/42 ,  H04L7/04

Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

公开(公告)号：PL350160A1

公开(公告)日：2002-11-18

申请号：PL35016000

申请日：2000-03-03

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES

IPC: G06F13/38 ,  G06F13/42 ,  H04L7/04

Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

公开(公告)号：HU0200283A2

公开(公告)日：2002-05-29

申请号：HU0200283

申请日：2000-03-03

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES

IPC: G06F13/42 ,  G06F5/06 ,  H04L7/00 ,  H04L7/02

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.