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    21.
    发明专利
    未知

    公开(公告)号：DE69512459D1

    公开(公告)日：1999-11-04

    申请号：DE69512459

    申请日：1995-04-07

    Applicant: IBM

    Inventor： FRANASZEK PETER ANTHONY ,  ROBINSON JOHN TIMOTHY ,  THOMASIAN ALEXANDER

    IPC: G06F3/06 ,  G06F11/10 ,  G06F12/08

    Abstract: A system for writing data to a disk array includes a cache memory coupled to the disk array for storing data indicative of locations on the disk array and parity blocks associated with parity groups including the locations. Each of the parity blocks includes an identifier indicative of locations within a particular parity group which are protected by the parity data. Write logic reads the identifier from the parity block, and based thereon, determines whether a disk location is not protected by the parity data. The write logic also writes to the location and updates the parity data and the identifier associated with the parity block to include the location of the data block to indicate that the location is protected.

    25.
    发明专利
    未知

    公开(公告)号：DE69021790D1

    公开(公告)日：1995-09-28

    申请号：DE69021790

    申请日：1990-06-11

    Applicant: IBM

    Inventor： FRANASZEK PETER ANTHONY

    IPC: G06F15/173 ,  H04Q11/04 ,  H04Q3/42 ,  H04Q3/68

    Abstract: A multistage network for the interconnection of parallel computers, having a combination of low latency and probability of blockage, without buffers, provide multiple return paths, used for example in a time-division-multiplexed (TDM) fashion. In addition, networks associated with the backward paths are used as a means of controlling the data transport, which permits the data transport function to be substantially simplified and also permits higher utilization of the data transport paths, as the control function can be pipelined.

    27.
    发明专利
    未知

    公开(公告)号：DE2225977A1

    公开(公告)日：1973-01-18

    申请号：DE2225977

    申请日：1972-05-27

    Applicant: IBM

    Inventor： FRANASZEK PETER ANTHONY

    IPC: H04B14/06 ,  H04J3/12 ,  H04J3/16

    Abstract: The principal feature of this multiplexed delta modulation system is its ability to introduce digital data or other low-frequency information signals into a high-frequency digitized signal stream at random times, without loss of synchronization or undue degradation of the high-frequency signal. When a low-frequency data bit is to be introduced into a bit stream representing the high-frequency signal, such a bit first is converted into a multibit code word W1 or W2, depending upon whether a 1 or 0 data bit is to be transmitted. The code word W1 or W2 they may be inserted into the transmitted bit stream at any random time, replacing a bit pattern of corresponding length in said stream which otherwise would represent the coincident portion of the high-frequency signal. The code word W1 or W2 is recognized as a data bit representation at the receiver regardless of where it occurs in the bit stream. If a bit pattern identical with W1 or W2, but not representing a low-frequency data bit, should appear by change in the high-frequency digitized signal, such a bit pattern is altered prior to its transmission so that it will not be mistaken for a data bit at the receiver. The delta modulation process automatically is adjusted to compensate for: (1) any difference between the numerical weight of an introduced bit pattern W1 or W2 and the numerical weight of the bit pattern which it replaces, or (2) in the case of a bit pattern fortuitously identical with W1 or W2, the difference between the respective numerical weights of such a bit pattern before and after its alteration.

    28.
    发明专利
    未知

    公开(公告)号：DE2227148A1

    公开(公告)日：1973-01-04

    申请号：DE2227148

    申请日：1972-06-03

    Applicant: IBM

    Inventor： FRANASZEK PETER ANTHONY

    IPC: G11B20/14 ,  H03M7/40 ,  H03M7/42 ,  G06F5/00

    Abstract: This is a run-length-limited, variable-length coding scheme which reduces the implementation needed to perform encoding and decoding functions and which limits the propagation of framing errors caused by incorrect coding or faulty bit detection. All code words utilized in this scheme are constrained to have distinctive word-ending bit sequences. Word-ending tests are performed repeatedly at strategic points in the bit stream in order to detect bit patterns that may denote word endings, and framing decisions are based upon these tests. Decoding functions are suspended while each new code word or frame is being serially entered into the input register for decoding. Where misframing occurs due to the presence of an erroneous bit in a code word, the propagation of such a framing error through subsequent words is limited by the fact that subsequent word-ending tests are performed independently of the framing decisions that preceded them, and also due to the fact that the average code word length is much less than in a fixed-length code system. Synchronism is quickly restored upon detecting a valid word-ending bit pattern following the erroneous bit. While the code words are of variable length, the rate of data transmission is constant due to a fixed ratio between the number of original data bits and the corresponding encoded data bits.

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