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    SYSTEMS AND METHODS FOR MASKING LATENCY OF MEMORY REORGANIZATION WORK IN A COMPRESSED MEMORY SYSTEM
    2.
    发明申请
    SYSTEMS AND METHODS FOR MASKING LATENCY OF MEMORY REORGANIZATION WORK IN A COMPRESSED MEMORY SYSTEM 审中-公开
    用于掩蔽压缩存储器系统中存储器重组延迟的系统和方法

    公开(公告)号：WO2008030672A3

    公开(公告)日：2008-05-08

    申请号：PCT/US2007074721

    申请日：2007-07-30

    Applicant: IBM ,  DALY DAVID MICHAEL ,  FRANASZEK PETER ANTHONY ,  IGNATOWSKI MICHAEL ,  LASTRAS-MONTANO LUIS ALFONSO ,  TROMBLEY MICHAEL RAYMOND

    Inventor： DALY DAVID MICHAEL ,  FRANASZEK PETER ANTHONY ,  IGNATOWSKI MICHAEL ,  LASTRAS-MONTANO LUIS ALFONSO ,  TROMBLEY MICHAEL RAYMOND

    IPC: G06F12/08

    CPC classification number: G06F12/08 ,  G06F12/0804 ,  G06F12/1408 ,  G06F2212/401

    Abstract: Computer memory management systems and methods are provided hi which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory, to particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory.reorganization work to allow resources to be used for serving new memory access requests and other high priority commands. In one aspect, a computer system ( 10) includes a main memory ( 160) comprising first (161) and second (162) memory' regions having different access characteristics, a memory controller (130) to manage the main memory (160) and to allow access to stored data items in the main memory (160), wherein the memory controller ( 130) implements a memory reorganization process comprising an execution flow of process steps for accessing a data hem that is stored in one of the first (161) or second memory region (162), and storing the accessed data item in the other one of the first (161) or second (162) memory region, and a local buffer memory (150) operated under control of the memory controller (130) to temporarily buffer data items to be written to the main memory (160) and data items read from the main memory (160) during the memory reorganization process, wherein the memory controller (130) temporarily suspends the execution flow of the memory reorganization process between process steps, if necessary, according to a priority schedule, and utilizes the local buffer memory (150) to temporarily store data that is to be processed when the memory reorganization process is resumed

    Abstract translation: 提供计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩蔽与访问压缩主存储器之后的存储器重组工作相关的等待时间，特别是数据块缓冲器和优先级调度协议 实现延迟和优先化memory.reorganization工作，以允许资源用于服务新的内存访问请求和其他高优先级命令。 在一个方面中，一种计算机系统（10）包括：主存储器（160），其包括具有不同访问特性的第一存储区（161）和第二存储区（162）;管理主存储器（160）的存储器控​​制器（130）;以及 以允许访问主存储器（160）中存储的数据项，其中存储器控制器（130）实现存储器重组过程，该存储器重组过程包括用于访问存储在第一（161）中的一个中的数据卷边的处理步骤的执行流程， 或第二存储器区域（162）中，并且将访问的数据项存储在第一（161）或第二（162）存储器区域中的另一个中，以及在存储器控制器（130）的控制下操作的本地缓冲存储器（150） 在存储器重新组织过程期间临时缓存要写入主存储器（160）的数据项和从主存储器（160）读取的数据项，其中存储器控制器（130）暂时中止存储器重组过程的执行流程 过程步骤，i f根据优先级调度表，并且利用本地缓冲存储器（150）临时存储当恢复存储器重组过程时要处理的数据

    8.
    发明专利
    未知

    公开(公告)号：DE69021790T2

    公开(公告)日：1996-04-18

    申请号：DE69021790

    申请日：1990-06-11

    Applicant: IBM

    Inventor： FRANASZEK PETER ANTHONY

    IPC: G06F15/173 ,  H04Q11/04 ,  H04Q3/42 ,  H04Q3/68

    Abstract: A multistage network for the interconnection of parallel computers, having a combination of low latency and probability of blockage, without buffers, provide multiple return paths, used for example in a time-division-multiplexed (TDM) fashion. In addition, networks associated with the backward paths are used as a means of controlling the data transport, which permits the data transport function to be substantially simplified and also permits higher utilization of the data transport paths, as the control function can be pipelined.

    9.
    发明专利
    未知

    公开(公告)号：DE3586035D1

    公开(公告)日：1992-06-17

    申请号：DE3586035

    申请日：1985-10-23

    Applicant: IBM

    Inventor： ADLER ROY LEE ,  FRANASZEK PETER ANTHONY ,  HASSNER MARTIN ,  SCHNEIDER RICHARD CRANE

    IPC: H03M7/14 ,  G06T9/00 ,  G11B20/14 ,  H03M5/14 ,  H03M13/23 ,  H04L25/497 ,  G11B20/10 ,  H04L25/49

    Abstract: The present invention relates to apparatus for encoding and decoding a stream of randomly distributed binary bits representing digital data of the type comprising encoding means (10) for encoding the stream of binary bits, recording means (18) for recording representations of the encoded stream of binary bits and recovery means (20, 25) for recovering timing signals and a stream of data signals from the recorded representations. … The apparatus is characterised in that the encoding means (10) achieves a run length limited, partial response coding of the data stream, and the recovery means comprises a first partial response decoder (20) for recovering a timing signal from the recorded representations, and a second partial response decoder (22) and a constrained decoder (24) means for recovering a stream of data signals from the recorded representations. … The present invention also relates to a method of encoding and decoding a stream of randomly distributed binary bits representing digital data using apparatus as above.

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