公开(公告)号：CA953032A

公开(公告)日：1974-08-13

申请号：CA130046

申请日：1971-12-14

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  PRICER WILBUR D

IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00

Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

公开(公告)号：CA1120610A

公开(公告)日：1982-03-23

申请号：CA336936

申请日：1979-10-03

Applicant: IBM

Inventor： HO IRVING T ,  RISEMAN JACOB

IPC: H01L21/22 ,  H01L21/033 ,  H01L21/225 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/336 ,  H01L29/78 ,  H01L21/461

Abstract: METHOD FOR FORMING DIFFUSIONS HAVING NARROW DIMENSIONS A method for forming diffusions having narrow, for example, submicrometer dimensions in a silicon body which involves forming insulator regions on a silicon body, which insulator regions have substantially horizontal surfaces and substantially vertical surfaces. A layer having a desired dopant concentration is formed thereon, both on the substantially horizontal surfaces and the substantially vertical surfaces. Reactive ion etching of the layer acts to substantially remove only the horizontal layer and provides a narrow dimensioned layer having a desired dopant concentration in the substantially vertical surfaces. Heating of the body at a suitable temperature is accomplished so as to produce the movement of the dopant into the silicon body by diffusion to form diffusions having narrow, such as submicrometer dimensions, therein. FI9-78-024

公开(公告)号：CA1120609A

公开(公告)日：1982-03-23

申请号：CA336935

申请日：1979-10-03

Applicant: IBM

Inventor： HO IRVING T ,  RISEMAN JACOB

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78

Abstract: METHOD FOR FORMING A NARROW DIMENSIONED MASK OPENING ON A SILICON BODY A method for forming a narrow, such as a submicrometer, dimensioned mask opening on a silicon body involving forming a first insulator region having substantially a horizontal surface and a substantially vertical surface. A second insulator is applied on both the the horizontal surface and substantially vertical surfaces. The second insulator is composed of a material different from that of the first insulator layer. Reactive ion etching of the second layer removes the horizontal layer and provides a narrow dimensioned second insulator region on the silicon body. The surface of the silicon body is then thermally oxidized. The narrow dimensioned second insulator region is removed to form a narrow dimensioned mask opening. FI9-78-023

公开(公告)号：CA1003119A

公开(公告)日：1977-01-04

申请号：CA173854

申请日：1973-06-12

Applicant: IBM

Inventor： HO IRVING T ,  RISEMAN JACOB

IPC: G06F12/08 ,  B23D45/00 ,  G06F13/00 ,  G11B20060101 ,  G11C7/00 ,  G11C11/00 ,  G11C11/40

公开(公告)号：CA996261A

公开(公告)日：1976-08-31

申请号：CA166916

申请日：1973-03-13

Applicant: IBM

Inventor： HO IRVING T ,  MALEY GERALD A ,  YU HWA N

IPC: G11C17/00 ,  G11C7/20 ,  G11C11/35 ,  G11C11/404 ,  G11C17/12 ,  H01L27/108

Abstract: A latent image memory is selectively operable as either a read-write memory or a read-only memory. The memory comprises an array of cells each preferably consisting of a single active device. A first set of the cells are each adapted to store either one of two binary digits. A second set of the cells are each responsive to a first condition for storing either one of two binary digits and responsive to a second condition for storing only a single predetermined binary digit. Means are provided for selecting either the first condition to render the array operable as a read-write memory, or the second condition to render the array operable as a read-only memory. Each of the cells of the first set preferably comprises a field-effect transistor connected to a capacitor, and each of the cells of the second set preferably comprises a charge-coupled device.

公开(公告)号：CA982238A

公开(公告)日：1976-01-20

申请号：CA173855

申请日：1973-06-12

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  YU HWA N

IPC: G11C27/04 ,  G06F3/00 ,  G06F12/00 ,  G11C19/28 ,  H01L21/339 ,  H01L27/105 ,  H01L29/762

公开(公告)号：CA980911A

公开(公告)日：1975-12-30

申请号：CA193154

申请日：1974-02-21

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  PRICER WILBUR D

公开(公告)号：CA1081803A

公开(公告)日：1980-07-15

申请号：CA268741

申请日：1976-12-24

Applicant: IBM

Inventor： HENLE ROBERT A ,  HO IRVING T

IPC: H03F3/345 ,  H03F3/34 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/0944 ,  H03K3/353 ,  H03K5/159

Abstract: OPTIMAL DRIVER FOR LSI An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=lnM, M = , and where the capacitance of any intermediate stage is . Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.

公开(公告)号：CA1057418A

公开(公告)日：1979-06-26

申请号：CA268530

申请日：1976-12-22

Applicant: IBM

Inventor： HO IRVING T ,  RISEMAN JACOB

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/78 ,  H01L29/34 ,  H01L21/70

Abstract: COMPOSITE CHANNEL FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION An improved composite channel field effect transistor and method of fabrication, which exhibits high density characteristics and yields high performance with less sensivity to threshold shift due to hot electrons when operated at high source to drain voltage levels.

公开(公告)号：FR2337428A1

公开(公告)日：1977-07-29

申请号：FR7636401

申请日：1976-11-29

Applicant: IBM

Inventor： HO IRVING T ,  RISEMAN JACOB

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/78 ,  H01L21/74

Abstract: An improved composite channel field effect transistor and method of fabrication, which exhibits high density characteristics and yields high performance with less sensivity to threshold shift due to hot electrons when operated at high source to drain voltage levels.