公开(公告)号：JP2010267064A

公开(公告)日：2010-11-25

申请号：JP2009117642

申请日：2009-05-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KATAOKA MASAKI ,  KOMATSU HIDEAKI

IPC: G06F9/48

CPC classification number: G06F13/24

Abstract: PROBLEM TO BE SOLVED: To prevent the influence of other calls, interrupts, exceptions and the like when a value of an interrupt mask register in an embedded system or the like is changed. SOLUTION: The architecture of a CPU is changed so that the content of the interrupt mask register can be changed directly according to the result of decoding an instruction decoder of the CPU. Normally, the change does not require a lot of time and effort in changing the design of the CPU. An extended CALL instruction and an extended software interrupt instruction are added to the CPU. The extended CALL instruction and the extended software interrupt instruction also have the function of changing the value of the interrupt mask register. The single instruction simultaneously calls a process and changes the value of the interrupt mask register, and atomicity is achieved by disabling interrupts during execution of the single instruction. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了防止在嵌入式系统等中的中断屏蔽寄存器的值改变时的其他调用，中断，异常等的影响。 解决方案：改变CPU的结构，使得可以根据对CPU的指令解码器的解码结果直接改变中断屏蔽寄存器的内容。 通常情况下，更改CPU的设计不需要花费大量的时间和精力。 扩展CALL指令和扩展软件中断指令被添加到CPU。 扩展CALL指令和扩展软件中断指令也具有改变中断屏蔽寄存器值的功能。 单个指令同时调用一个进程并改变中断屏蔽寄存器的值，并且通过在执行单个指令期间禁用中断来实现原子性。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010134847A

公开(公告)日：2010-06-17

申请号：JP2008312345

申请日：2008-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KONDO TAKESHI ,  KOMATSU HIDEAKI

IPC: G06F11/28

Abstract: PROBLEM TO BE SOLVED: To provide a code generation technique which adapt a code to dynamically modified profile information in response to the modification of profile information. SOLUTION: System configuration information is obtained. In dependence on it, a load process and a store process are performed, where they are called LoadX and StoreX, respectively. On the other hand, normal load process and store process are called load and store, respectively. Accordingly, the invention assumes a system configuration for each compile unit. Under this assumption, a load/store instruction for finding access to the normal RAM/ROM is converted not into the LoadX/StoreX instruction into the normal load/store instruction. This brings an optimization effect to compiling. An execution code obtained above is systematically registered in a two-dimensional table with an start address of a guest and an index of system configuration information as a key. This allows an optimization code obtained by searching the table to be executed in execution. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种代码生成技术，其适应代码以响应于简档信息的修改来动态地修改简档信息。

解决方案：获取系统配置信息。 依赖于它，执行加载进程和存储进程，分别称为LoadX和StoreX。 另一方面，正常的负载过程和存储过程分别称为加载和存储。 因此，本发明假设每个编译单元的系统配置。 在这种假设下，用于查找访问正常RAM / ROM的加载/存储指令不会转换为LoadX / StoreX指令到正常的加载/存储指令。 这给编译带来了优化效果。 上面获得的执行代码被系统地注册在具有来宾的起始地址和系统配置信息的索引作为关键字的二维表中。 这允许通过搜索在执行中执行的表获得的优化代码。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010002968A

公开(公告)日：2010-01-07

申请号：JP2008158995

申请日：2008-06-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHIMIZU SHUICHI ,  KOMATSU HIDEAKI ,  KAJITANI KOICHI

IPC: G06F9/54 ,  G06F11/28 ,  G06F19/00

Abstract: PROBLEM TO BE SOLVED: To efficiently simulate a system having a plurality of different types of ECU by software. SOLUTION: Each ECU emulator is speculatively emulated. That is, when the ECU emulator or each physical device simulator is called as a logical process, any critical path is not created, and each logical process is executed in parallel as much as possible, and even when any input event is not delivered in each logical process, the input is predicted, and the processing is advanced. This speculative execution makes it possible to previously execute processing without waiting for the output of another logical process so that the parallelism of processing can be increased. When the actual input to be received with delay is not matched with the predicted and speculatively executed input, it is determined that the speculative execution fails, and the status is returned to the previous time, and the processing is re-executed based on the actual input. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：通过软件有效地模拟具有多种不同类型的ECU的系统。

解决方案：每个ECU仿真器都被推测模拟。 也就是说，当ECU模拟器或每个物理设备模拟器被称为逻辑进程时，不会创建任何关键路径，并且每个逻辑进程尽可能并行地执行，并且即使当每个逻辑进程中的任何输入事件不在每个 逻辑过程，预测输入，并提前处理。 这种推测执行使得可以预先执行处理而不等待另一个逻辑进程的输出，使得可以增加处理的并行性。 当要延迟接收的实际输入与预测和推测执行的输入不匹配时，确定推测执行失败，并将状态返回到上一次，并根据实际情况重新执行处理 输入。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008142137A

公开(公告)日：2008-06-26

申请号：JP2006330025

申请日：2006-12-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBARA MORIMIKI ,  INOUE HIROSHI ,  KOMATSU HIDEAKI

IPC: A61B6/03 ,  A61B5/055 ,  A61B6/00 ,  G06T7/00

Abstract: PROBLEM TO BE SOLVED: To provide a data processing apparatus, a data processing method, and a program for aligning three-dimensional images. SOLUTION: The data processing apparatus 10 is equipped with down sample processing means 44-48 for lowering the resolution of a fixed image 40, first registering means (50, 52) for performing a registration between the fixed image with the resolution lowered by the down sample processing means 44-48 and the moving image with the lowered resolution like the fixed image with the lowered resolution, and second registering means (54, 56) for performing the registration of the fixed image with the lowered resolution and the moving image with the lowered resolution by using a linear transformation parameter output by the first registering means 52 as an initial value and stores pixel data to be used for the calculation of the mutual information volume in a main memory in a manner to be continuously accessed to execute by fetching the pixel data in a local memory. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供数据处理装置，数据处理方法和用于对准三维图像的程序。 解决方案：数据处理装置10配备有用于降低固定图像40的分辨率的下采样处理装置44-48，用于在降低分辨率的固定图像之间执行对准的第一登记装置（50,52） 通过下采样处理装置44-48和具有降低的分辨率的降低的分辨率的运动图像与分辨率降低的固定图像相关联;以及第二登记装置（54,56），用于以降低的分辨率和移动的方式执行固定图像的登记 通过使用由第一登记装置52输出的线性变换参数作为初始值，降低分辨率的图像，并且以将被连续访问的方式存储在主存储器中用于计算互信息量的像素数据以执行 通过在本地存储器中获取像素数据。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004021336A

公开(公告)日：2004-01-22

申请号：JP2002171856

申请日：2002-06-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOSEKI SATOSHI ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/441

Abstract: PROBLEM TO BE SOLVED: To allocate a proper register to a plurality of variables by solving the problem of delaying an execution speed of a generating command train since a variable using method is not adapted to properties of registers allocated to the variables in a computer mutually different in the respective properties of a plurality of registers. SOLUTION: This compiler converts a source program into the command train of a processor, and is provided with a simultaneously using variable acquiring part 220 for acquiring a variable simultaneously used with the variables in a plurality of respective variables used in the source program, an allocation order forming part 230 for forming a plurality of allocation orders between the plurality of variables allocated to the registers different from a variable simultaneously used with the variables, an allocation precedence acquiring part 300 for acquiring allocation precedence for indicating to which register the plurality of respective variables are preferentially allocated among the plurality of registers and a register allocation part 310 for allocating the plurality of variables to the registers according to one allocation order selected on the basis of the allocation precedence among the plurality of allocation orders. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002091777A

公开(公告)日：2002-03-29

申请号：JP2000276203

申请日：2000-09-12

Applicant: IBM

Inventor： KOSEKI SATOSHI ,  KOMATSU HIDEAKI

IPC: G06F9/45

Abstract: PROBLEM TO BE SOLVED: To realize an efficient compile by decreasing the number of interference between variables while guaranteeing the possibility of the parallel execution of instruction in graph coloring. SOLUTION: The compiler for translating the source code of a program described in a programming language into a machine word and optimizing the program, is provided with a DAG analyzing part 11 for constructing and analyzing the DAG of an instruction from the program as a processing target, an interference graph constructing part 12 for constructing an interference graph showing the presence/absence of interference between variables to be used for this instruction on the basis of the analyzed result and a graph coloring part 13 for performing register assignment to this instruction based on the constructed interference graph and when the running time of this entire program is to be extended without parallel executing prescribed plural instructions, this interference graph constructing part 12 constructs the interference graph by deciding that these plural instructions interfere the variables to be used.

公开(公告)号：JP2001154853A

公开(公告)日：2001-06-08

申请号：JP32699099

申请日：1999-11-17

Applicant: IBM

Inventor： YASUE TOSHIAKI ,  OGATA KAZUNORI ,  ISHIZAKI KAZUAKI ,  KOMATSU HIDEAKI

IPC: G06F9/45

Abstract: PROBLEM TO BE SOLVED: To provide a program execution method for realizing much higher level optimization. SOLUTION: A program executing device 1 realizes transition between a compile processing and interpreter processing in the middle of the execution of a method. When there is not any problem on execution even if moving a transition point to the entrance of a loop, the transition point of a code is moved to the entrance of a loop, and when the transition point is positioned inside the loop, a point for post dominating the entrance of the loop and the transition point is copied just before the loop. Thus, the transition point is allowed to have information for generating a re-calculation code so that re- execution can be executed.

公开(公告)号：JPH11175349A

公开(公告)日：1999-07-02

申请号：JP30821297

申请日：1997-11-11

Applicant: IBM

Inventor： OGATA KAZUNORI ,  KOMATSU HIDEAKI ,  MOMOSE HIROYUKI

IPC: G06F9/45 ,  G06F9/455

Abstract: PROBLEM TO BE SOLVED: To provide a compiler capable of executing the byte code of Java at a high speed with limited resources. SOLUTION: The byte code 14 is converted to an intermediate code 102 whose operation code is the address of processing routines corresponding to the respective byte codes and the processing routines are executed in the order of the intermediate codes. At the time, the intermediate code is turned to a fixed length and the bit position of the operation code is also fixed in it. Also, the processing routines are arranged in successive areas on a memory and an offset from the leading address of a processing routine group 104 is used for the operation code. Further, the vacancy of the pipeline of a CPU is utilized and a part (generation of operand and jump) of an instruction group for jumping to the processing routine of the next intermediate code and a part (pre-fetch of intermediate code and address calculation of processing routine) of the instruction group for jumping to the processing routine of the intermediate code after the next are executed parallelly to the original processing for the intermediate code.

公开(公告)号：JPH09319722A

公开(公告)日：1997-12-12

申请号：JP12806596

申请日：1996-05-23

Applicant: IBM

Inventor： SUGANUMA TOSHIO ,  KOMATSU HIDEAKI

IPC: G06F15/16 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To fast run a compiled object program by extracting correctly the reduction, i.e., a loop pattern that frequently appears in a source program out of this source program. SOLUTION: The reduction is detected out of a loop (Step 21) and then converted into a loop that can be carried out effectively and in parallel (Step 22). Finally, the reduction communication is generated based on the converted loop and optimized (Step 23). The detection of reduction consists of three sub- steps. That is, a model is first produced in regard to the mask expression masking every substitute sentence in the loop. In other words, an expression tree concerning the execution condition of every substitute sentence is generated. Then it's decided whether the reduction consists of an expression tree of merged substitute sentences based on the expression tree of a prescribed conditional expression and also the data dependence relation.

公开(公告)号：JP2011118841A

公开(公告)日：2011-06-16

申请号：JP2009278002

申请日：2009-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKAHASHI HITOMI ,  CHO KO ,  KOMATSU HIDEAKI

IPC: G05B17/02

CPC classification number: G06F17/5009 ,  G05B13/04 ,  G05B17/00 ,  G05B19/406 ,  G05B19/4061 ,  G05B19/4063 ,  G05B23/0205 ,  G05B23/0243 ,  G06F1/03 ,  G06F8/34 ,  G06F11/3668 ,  G06F17/10

Abstract: PROBLEM TO BE SOLVED: To provide a technique for efficiently testing stability by avoiding a combinatorial explosion regardless of the number and quality of nonlinear blocks when switched linearization is utilized for a simulation system including a plurality of nonlinear blocks to form a system having a plurality of states.
SOLUTION: When the states are changed according to an operation scenario and the following state is not attained yet, the simulation system places a software guard 1202 showing that the state is not attained. In response to encountering the guard, whether the state is safe or not is tested.When the state is safe, the simulation system deletes the guard and places another guard at the next state. On the other hand, when the state is unstable, the simulation system replaces the guard by an unstable guard 1204. Then, it records an appearance state of a transition, and suitably ends the simulation.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于通过避免组合爆炸来有效测试稳定性的技术，而不管非线性块的数量和质量如何，当切换​​线性化用于包括多个非线性块的模拟系统以形成具有 多个状态。 解决方案：当根据操作场景改变状态并且还没有获得以下状态时，仿真系统放置示出未达到状态的软件保护装置1202。 对于遇到守卫，无论国家是否安全，都要进行测试。国家安全的情况下，模拟系统会将守卫删除，并在下一个状态下放置另一个卫兵。 另一方面，当状态不稳定时，模拟系统用不稳定的保护装置1204代替防护装置。然后，记录转移的外观状态，适当地结束模拟。 版权所有（C）2011，JPO＆INPIT