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公开(公告)号：GB767236A
公开(公告)日：1957-01-30
申请号：GB3045754
申请日：1954-10-22
Applicant: IBM
Inventor： LENTZ JOHN J
Abstract: 767,236. Digital electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 22,1954 [Oct. 26, 1953], No. 30457/54. Class 106 (1). A digital electrical computer comprises a moving carrier adapted to store digital information supplied in the form of pulses differentially spaced in time and having a reading head connected to an assoicated recording head by two circulation paths for information flow between said heads, the first of said paths comprising delay means and the second of said paths comprising counting circuit means, comparing means adapted to compare digital information flowing respectively in said first and second circulating paths, and control means associated with said first and second circulating paths for controlling the flow of information therethrough. The invention is described as applied to a keyboard controlled computer having storage capacity for four decimal numbers A, B, C and D, the numbers A and B each having 15 digits plus a sign digit and the numbers C and D each having 30 digits plus a sign digit, for performing the one calculation A/B Î C + D, which it does in the following steps (1) during the first major cycle the number in the A register is replaced by A-B, and the number in the D register is replaced by C + D; this is repeated for following major cycles until A is less than B. (2) In the major cycle immediately after the cycle in which a number less than B is placed in the A register, the number in the A register is multiplied by 10, by a shift, and the number in the C register is divided by 10, also by a shift. (3) Steps (1) and (2) are then repeated until 15 shifts have been made the number then in the D register being the first 15 digits of the result. (30 digits can be obtained by continuing the process for 30 shifts.) Representation of numbers and storage registers. The four registers are constituted by a single track on a magnetic drum, Fig. 1, the digits of the C and D registers and the B and A registers being interlaced as shown in the order CO, DO, C1, D1 ... C29, D29, C30, D30, B0, A0 ... B15, A15 syn, syn, the digits labelled " syn " being for synchronizing purposes. Two digits are said to occupy a " box " which is also taken as the unit of time for the computer, a time of one box being the time taken for one box to pass the reading head 27. The speed of the computer is therefore primarily determined by the drum speed and all operations are controlled by pulses generated under the control of a master or base oscillator synchronized to the speed of the drum. Within each half-box (equals one digit) a decimal number is represented by one differentially positioned pulse in one of ten " cells " 0 to 9, as shown for digit D2, the remaining two cells T and P being used for synchronizing purposes. The highest order digit of each number represents the sign of the number, positive numbers being represented in their true form with a sign digit of 0 and negative numbers being represented as their tens complement, which is defined as their nines complement with the addition of unity, with a sign digit of 9. Basic layout and operation of the machine. Data on the drum is continually being read, by a reading head 27, Fig. 2, processed and rerecorded by a writing head 26 one box later, the writing head being positioned 47 boxes before the reading head so that any particular box is always read at the same time in a cycle of 48 boxes (A and B registers 16 boxes, C and D registers 31 boxes, synchronization one box). The path taken by information when the computer is idling (that is when no calculations are taking place) is shown symbolically in Fig. 2 in which the illustrated switches are actually diode gating circuits, and is from drum 25 to a switching unit 50, which separates the two digits of one box, and then either via two half-box delays 29, 30 and back to the drum or via an add/subtract arithmetic unit 34 and a half-box delay 31 and back to the drum, the arithmetic unit being set at " add ". The entry of all numbers which may be positive or negative, is done via a switch 46 and the arithmetic unit 34. The numbers in the B and A, or C and D registers can be interchanged by closing switches 41, 42 and 43. The A number then flows via delay 30 back to the drum, experiencing only one half-box delay and the B number flows via delay 29, arithmetic unit 34, and delay 31 and back to the drum experiencing one and a half boxes delay and thus the A and B numbers are interchanged. A In step (1) of the calculation - x C + D, the B number C is fed from delay 29 via delay 30 and back to the drum and also via switch 45 to the second input of the arithmetic unit where it is added to D and the sum passes via delay 31 to the drum; the B number follows the same path but the arithmetic unit is set for subtraction so that the difference of A and B is fed to the drum. As the difference A-B is being fed to the drum it is compared with the number B by a comparer 35 and depending upon whether or not B is less than A-B the comparer either causes the same operation to be repeated or a shift to be performed respectively. The arithmetic unit. The basic unit of the arithmetic unit is a capacitor decimal counter 91, Fig. 8. Each input pulse to be counted, applied at terminal 92 via an " or " gate 108, causes pentode 141 to conduct, partially discharging a condenser 142. After 10 input pulses the voltage on condenser 142 will have dropped to such a value that the right-hand side of a double triode 148 will conduct creating a negative pulse which changes over a bi-stable trigger circuit 156, which in turn gives a positive output pulse at terminal 93 via a cathode follower 157. The changing over of trigger circuit 156, which is immediately reset by a pulse from a gate 162, also applies a negative pulse to a triode 159, which recharges the capacitor 142 via the right-hand diode 161, the voltage across the capacitor 142 being limited to 100 v. by a cathode follower 163 and the left-hand diode 161. Thus the counter automatically resets itself. The inputs applied to a gate 108 via leads 124 and 107 are gated bursts of two interlaced types of clock pulses representative of the numbers to be added. These bursts are applied during a " read in " cycle lasting half a box and if during this read in cycle an output is produced at terminal 93, indicating that the sum of the two digits being added exceeds 10, a carry storage trigger 131 is set by a pulse from " and " gate 242. During the next half-box, the " read-out " cycle, further pulses are applied via lead 107 to the counter until an output results, the timing of which will represent the digit previously stored in the counter. At the beginning of the next read in cycle, if trigger 131 is storing a carry it would cause a single pulse to be passed to the counter via a gate 133, and will then be reset. After this single pulse (if present) bursts of pulses to be added will be applied as before. As previously stated negative numbers are represented as their tens complements and are handled as positive numbers. For subtraction, the gates applying the bursts of pulses to be counted are caused to supply complements on nines and a fugitive one is added by the carry circuit. The comparer unit. Since individual digits are represented by differentially timed pulses, as shown in Fig. 1, two digits can be compared for equality by observing which of the pulses representing them occurs last. This is done by triodes 180, 181 and diodes 184, 185, Fig. 9, the digit representing pulses being applied at terminals 175, 176. Initially the cathodes of diodes 184, 185 are at - 50 v. (this state being produced by a triode 92 which is made momentarily conductive). The arrival of the first pulse, say on terminal 175, renders triode 180 conductive, raising the cathode of diode 184 to 0 volts and charging the condenser 188, the cathode of diode 185 rising in potential momentarily while the pulse is present but immediately falling back to - 50 v. at the end of the pulse. On the arrival of the pulse at terminal 176, representing the second smaller digit, the upper plate of condenser 188 is at ground potential and so a positive pulse is transmitted, via condenser 188, to trigger circuit 203 which is normally conductive on its right-hand side. Had the pulse on terminal 176 arrived first, then the pulse on terminal 175 would have resulted in a positive pulse being applied to the right-hand side of trigger circuit 203 via a cathode follower 208. The comparison of multi-digit numbers proceeds digit by digit in this way, the circuit 180, 181, 184, 185 being reset after each digit by tube 192, and the final state of trigger circuit 203 indicating which is the larger number.
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公开(公告)号：CA754758A
公开(公告)日：1967-03-14
申请号：CA754758D
Applicant: IBM
Inventor： LENTZ JOHN J , SEEBER ROBERT R JR
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Patent Agency Ranking
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公开(公告)号：DE1151959B
公开(公告)日：1963-07-25
申请号：DEJ0017995
申请日：1960-04-20
Applicant: IBM
Inventor： LENTZ JOHN J , SEEBER ROBERT R
Abstract: 931,057. Electrical digital data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 25, 1960 [April 30, 1959], No. 14352/60. Class 106 (1). A data storage system includes an entry register, a number of storage registers each accommodating data and " vacancy " information, and associated circuits responsive to the vacancy information to control the entry of new information into the registers. Vacancy information is the presence or absence of a character which indicates that no data is to replace the data associated with the character. With each data word also is associated a tag. All the tags are compared in parallel with a tag defined, the required data and the contents of the register holding this tag are read out on the successful comparison being made. As described the vacancy character is a single bit and the circuits comprise cryotron gates. Four types of gate are used differing only in the arrangement of the coils. The gate 2 becomes resistive when a current flows in its single coil; "A" gate 4 is an OR circuit becoming resistive when current is flowing in at least one of the coils; " B " gate 6 is an exclusive-or circuit becoming resistive when current is flowing in only one of the coils; and " C " gate 8 is superconductive if the centre coil and one of the other two coils, or if none of the coils are energized. Figs. 1A to 1D show a storage device including an entry register, two typical word registers and an exit register. The 0, 1 or ON, OFF markings indicate that a unit is storing the bit marked or is in the state marked, if the cryotron gate is superconductive. Read-in.-The data word including vacancy and tag bits is entered into the entry register by applying current to the coil of an appropriate one of the entry pair of each bit store. Thus a vacancy bit of is entered by applying current to the coil 12 which sends gate 14 resistive and permits current to flow through gates 16 and 18 and the coils 20, 24 to send the 0 gates resistive. For read-in the entry-exit bit is 0, and initially the timing signal is off. Under these conditions current flows from source 70, through gate 73, coils 74 and 76, 170 and 172 and similar coils in the order bit stores of the entry register. When the timing signal goes on the contents of the entry register are entered in a word register having a vacancy bit of 0. The value of a vacancy bit is reflected in a set of six cryotron gates-an echo bit set-which control the entry of information into a word register. With the timing signal on current from source 72 flows through gate 104, gate 126 to the lower pair of gates in the echo bit set of the first word register. If the vacancy bit is 1 the current flows through gate 300 and is applied to the echo bit set of the next register. If all registers have a vacancy bit of 1 coil 546 is energized and a no vacancy signal issues on terminal 562. If the vacancy bit is 0 in the first word register (say) current flows through gate 190, coil 192 of A-gate 150, coil 194 of C-gate 196 and coils 210, 212 . . . of entry B-gates of the word register. If, for example, tag bit t is 0, current flows through A gate 201, B-gate 242 and coil 260 which permits current to flow through gate 264 to render gate 394 resistive and energize one of the coils of the 1 C-gate. The new vacancy bit is entered at this time but is not entered in the echo bit set in order that it may not interfere with the entry of its own associated word. In fact, gate C is conductive and current energizes the coils 40 and 38 to result in gate 56 becoming resistive. When the timing signal goes off, current flows through gate 300, gate 302 and coil 304 to enter 1 in the echo bit set. Read-out.-The entry-exit bit is 1 and the required tag is entered in the entry register. It will be assumed that tag bit t is 1 and the tag of the first word register is also 1. With the timing signal off, current from source 72 flows through line 80 and the coils of the entry gates of the exit register while current from source 70 flows through entry register exit control line 78. With the timing signal on, current from source 72 passes through gate 140 to line 142 from where it is applied in parallel to B-gates 567, 569. If the word register tag bit is the same as that in the entry register the B-gate is conductive. Thus if current flows through gate 570 to coil 568 if the required tag bit is 1, and if the word tag bit is 1 current flows in coil 576 to render B-gate 569 conductive. After flowing through gate 292 current is applied to the next tag bit B-gate, and if it passes through all the B-gates is applied to the coils of the exit pair of C-gates, e.g. 272, 274. One of these gates in each bit position becomes conductive and the contents of the word register transferred to the exit register, line 80 no longer being energized. Note that current to line 78 is maintained with timing signal on since current from source 70 then flows through gate 102 and gate 139 to line 78, and that if the required tag bit is 0 and a word tag bit is 0 the B-gate is conductive since neither coil 568 nor coil 596 is energized. Magnetic cores or relays are mentioned as equivalent circuit components.
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公开(公告)号：DE1034889B
公开(公告)日：1958-07-24
申请号：DEI0009287
申请日：1954-10-23
Applicant: IBM
Inventor： LENTZ JOHN J
Abstract: 767,236. Digital electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 22,1954 [Oct. 26, 1953], No. 30457/54. Class 106 (1). A digital electrical computer comprises a moving carrier adapted to store digital information supplied in the form of pulses differentially spaced in time and having a reading head connected to an assoicated recording head by two circulation paths for information flow between said heads, the first of said paths comprising delay means and the second of said paths comprising counting circuit means, comparing means adapted to compare digital information flowing respectively in said first and second circulating paths, and control means associated with said first and second circulating paths for controlling the flow of information therethrough. The invention is described as applied to a keyboard controlled computer having storage capacity for four decimal numbers A, B, C and D, the numbers A and B each having 15 digits plus a sign digit and the numbers C and D each having 30 digits plus a sign digit, for performing the one calculation A/B Î C + D, which it does in the following steps (1) during the first major cycle the number in the A register is replaced by A-B, and the number in the D register is replaced by C + D; this is repeated for following major cycles until A is less than B. (2) In the major cycle immediately after the cycle in which a number less than B is placed in the A register, the number in the A register is multiplied by 10, by a shift, and the number in the C register is divided by 10, also by a shift. (3) Steps (1) and (2) are then repeated until 15 shifts have been made the number then in the D register being the first 15 digits of the result. (30 digits can be obtained by continuing the process for 30 shifts.) Representation of numbers and storage registers. The four registers are constituted by a single track on a magnetic drum, Fig. 1, the digits of the C and D registers and the B and A registers being interlaced as shown in the order CO, DO, C1, D1 ... C29, D29, C30, D30, B0, A0 ... B15, A15 syn, syn, the digits labelled " syn " being for synchronizing purposes. Two digits are said to occupy a " box " which is also taken as the unit of time for the computer, a time of one box being the time taken for one box to pass the reading head 27. The speed of the computer is therefore primarily determined by the drum speed and all operations are controlled by pulses generated under the control of a master or base oscillator synchronized to the speed of the drum. Within each half-box (equals one digit) a decimal number is represented by one differentially positioned pulse in one of ten " cells " 0 to 9, as shown for digit D2, the remaining two cells T and P being used for synchronizing purposes. The highest order digit of each number represents the sign of the number, positive numbers being represented in their true form with a sign digit of 0 and negative numbers being represented as their tens complement, which is defined as their nines complement with the addition of unity, with a sign digit of 9. Basic layout and operation of the machine. Data on the drum is continually being read, by a reading head 27, Fig. 2, processed and rerecorded by a writing head 26 one box later, the writing head being positioned 47 boxes before the reading head so that any particular box is always read at the same time in a cycle of 48 boxes (A and B registers 16 boxes, C and D registers 31 boxes, synchronization one box). The path taken by information when the computer is idling (that is when no calculations are taking place) is shown symbolically in Fig. 2 in which the illustrated switches are actually diode gating circuits, and is from drum 25 to a switching unit 50, which separates the two digits of one box, and then either via two half-box delays 29, 30 and back to the drum or via an add/subtract arithmetic unit 34 and a half-box delay 31 and back to the drum, the arithmetic unit being set at " add ". The entry of all numbers which may be positive or negative, is done via a switch 46 and the arithmetic unit 34. The numbers in the B and A, or C and D registers can be interchanged by closing switches 41, 42 and 43. The A number then flows via delay 30 back to the drum, experiencing only one half-box delay and the B number flows via delay 29, arithmetic unit 34, and delay 31 and back to the drum experiencing one and a half boxes delay and thus the A and B numbers are interchanged. A In step (1) of the calculation - x C + D, the B number C is fed from delay 29 via delay 30 and back to the drum and also via switch 45 to the second input of the arithmetic unit where it is added to D and the sum passes via delay 31 to the drum; the B number follows the same path but the arithmetic unit is set for subtraction so that the difference of A and B is fed to the drum. As the difference A-B is being fed to the drum it is compared with the number B by a comparer 35 and depending upon whether or not B is less than A-B the comparer either causes the same operation to be repeated or a shift to be performed respectively. The arithmetic unit. The basic unit of the arithmetic unit is a capacitor decimal counter 91, Fig. 8. Each input pulse to be counted, applied at terminal 92 via an " or " gate 108, causes pentode 141 to conduct, partially discharging a condenser 142. After 10 input pulses the voltage on condenser 142 will have dropped to such a value that the right-hand side of a double triode 148 will conduct creating a negative pulse which changes over a bi-stable trigger circuit 156, which in turn gives a positive output pulse at terminal 93 via a cathode follower 157. The changing over of trigger circuit 156, which is immediately reset by a pulse from a gate 162, also applies a negative pulse to a triode 159, which recharges the capacitor 142 via the right-hand diode 161, the voltage across the capacitor 142 being limited to 100 v. by a cathode follower 163 and the left-hand diode 161. Thus the counter automatically resets itself. The inputs applied to a gate 108 via leads 124 and 107 are gated bursts of two interlaced types of clock pulses representative of the numbers to be added. These bursts are applied during a " read in " cycle lasting half a box and if during this read in cycle an output is produced at terminal 93, indicating that the sum of the two digits being added exceeds 10, a carry storage trigger 131 is set by a pulse from " and " gate 242. During the next half-box, the " read-out " cycle, further pulses are applied via lead 107 to the counter until an output results, the timing of which will represent the digit previously stored in the counter. At the beginning of the next read in cycle, if trigger 131 is storing a carry it would cause a single pulse to be passed to the counter via a gate 133, and will then be reset. After this single pulse (if present) bursts of pulses to be added will be applied as before. As previously stated negative numbers are represented as their tens complements and are handled as positive numbers. For subtraction, the gates applying the bursts of pulses to be counted are caused to supply complements on nines and a fugitive one is added by the carry circuit. The comparer unit. Since individual digits are represented by differentially timed pulses, as shown in Fig. 1, two digits can be compared for equality by observing which of the pulses representing them occurs last. This is done by triodes 180, 181 and diodes 184, 185, Fig. 9, the digit representing pulses being applied at terminals 175, 176. Initially the cathodes of diodes 184, 185 are at - 50 v. (this state being produced by a triode 92 which is made momentarily conductive). The arrival of the first pulse, say on terminal 175, renders triode 180 conductive, raising the cathode of diode 184 to 0 volts and charging the condenser 188, the cathode of diode 185 rising in potential momentarily while the pulse is present but immediately falling back to - 50 v. at the end of the pulse. On the arrival of the pulse at terminal 176, representing the second smaller digit, the upper plate of condenser 188 is at ground potential and so a positive pulse is transmitted, via condenser 188, to trigger circuit 203 which is normally conductive on its right-hand side. Had the pulse on terminal 176 arrived first, then the pulse on terminal 175 would have resulted in a positive pulse being applied to the right-hand side of trigger circuit 203 via a cathode follower 208. The comparison of multi-digit numbers proceeds digit by digit in this way, the circuit 180, 181, 184, 185 being reset after each digit by tube 192, and the final state of trigger circuit 203 indicating which is the larger number.
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